1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 *                    Dave Liu <daveliu@freescale.com>
5 *
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 *                    Peter Barada <peterb@logicpd.com>
8 *
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 */
15
16#include <common.h>
17#include <env.h>
18#include <event.h>
19#include <fdt_support.h>
20#include <init.h>
21#include <ioports.h>
22#include <log.h>
23#include <mpc83xx.h>
24#include <i2c.h>
25#include <miiphy.h>
26#include <asm/global_data.h>
27#include <asm/io.h>
28#include <asm/mmu.h>
29#include <asm/processor.h>
30#include <pci.h>
31#include <linux/delay.h>
32#include <linux/libfdt.h>
33#include <post.h>
34
35#include "../common/common.h"
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#if CONFIG_IS_ENABLED(TARGET_KMCOGE5NE) || CONFIG_IS_ENABLED(TARGET_KMETER1)
40#define CFG_SYS_DDR_MODE	0x47860452
41#define CFG_SYS_DDR_INTERVAL (\
42	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
43	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
44#define CFG_SYS_DDR_TIMING_0 (\
45	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
46	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
47	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
48	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
49	(0 << TIMING_CFG0_WWT_SHIFT) | \
50	(0 << TIMING_CFG0_RRT_SHIFT) | \
51	(0 << TIMING_CFG0_WRT_SHIFT) | \
52	(0 << TIMING_CFG0_RWT_SHIFT))
53
54#define CFG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
55				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
56				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
57				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
58				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
59				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
60				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
61				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
62
63#define CFG_SYS_DDR_TIMING_2 (\
64	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
65	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
66	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
67	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
68	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
69	(5 << TIMING_CFG2_CPO_SHIFT) | \
70	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
71
72#define CFG_SYS_DDR_TIMING_3			0x00000000
73
74#else
75#define CFG_SYS_DDR_MODE	0x47860242
76#define CFG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
77				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
78
79#define CFG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
80				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
81				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
82				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
83				 (0 << TIMING_CFG0_WWT_SHIFT) | \
84				 (0 << TIMING_CFG0_RRT_SHIFT) | \
85				 (0 << TIMING_CFG0_WRT_SHIFT) | \
86				 (0 << TIMING_CFG0_RWT_SHIFT))
87
88#define CFG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
89				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
90				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
91				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
92				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
93				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
94				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
95				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
96
97#define CFG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
98				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
99				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
100				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
101				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
102				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
103				 (5 << TIMING_CFG2_CPO_SHIFT))
104
105#define CFG_SYS_DDR_TIMING_3	0x00000000
106
107#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
108					 CSCONFIG_ODT_WR_CFG | \
109					 CSCONFIG_ROW_BIT_13 | \
110					 CSCONFIG_COL_BIT_10)
111#endif
112
113#define CFG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
114					 SDRAM_CFG_32_BE | \
115					 SDRAM_CFG_SREN | \
116					 SDRAM_CFG_HSE)
117#define CFG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
118#define CFG_SYS_DDR_SDRAM_CFG2	0x00401000
119#define CFG_SYS_DDR_CS0_BNDS	0x0000007f
120#define CFG_SYS_DDR_MODE2	0x8080c000
121
122#define CFG_SYS_SDRAM_SIZE	0x80000000 /* 2048 MiB */
123
124static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
125
126static int piggy_present(void)
127{
128	struct km_bec_fpga __iomem *base =
129		(struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
130
131	return in_8(&base->bprth) & PIGGY_PRESENT;
132}
133
134int ethernet_present(void)
135{
136	return piggy_present();
137}
138
139int board_early_init_r(void)
140{
141	struct km_bec_fpga *base =
142		(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
143
144#if defined(CONFIG_ARCH_MPC8360)
145	unsigned short	svid;
146	/*
147	 * Because of errata in the UCCs, we have to write to the reserved
148	 * registers to slow the clocks down.
149	 */
150	svid =  SVR_REV(mfspr(SVR));
151	switch (svid) {
152	case 0x0020:
153		/*
154		 * MPC8360ECE.pdf QE_ENET10 table 4:
155		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
156		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
157		 */
158		setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
159		break;
160	case 0x0021:
161		/*
162		 * MPC8360ECE.pdf QE_ENET10 table 4:
163		 * IMMR + 0x14AC[24:27] = 1010
164		 */
165		clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
166			0x00000050, 0x000000a0);
167		break;
168	}
169#endif
170
171	/* enable the PHY on the PIGGY */
172	setbits_8(&base->pgy_eth, 0x01);
173	/* enable the Unit LED (green) */
174	setbits_8(&base->oprth, WRL_BOOT);
175	/* enable Application Buffer */
176	setbits_8(&base->oprtl, OPRTL_XBUFENA);
177
178	return 0;
179}
180
181int misc_init_r(void)
182{
183	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
184			CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
185	return 0;
186}
187
188static int last_stage_init(void)
189{
190#if defined(CONFIG_TARGET_KMCOGE5NE)
191	/*
192	 * BFTIC3 on the local bus CS4
193	 */
194	struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
195	u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
196
197	if (dip_switch != 0) {
198		/* start bootloader */
199		puts("DIP:   Enabled\n");
200		env_set("actual_bank", "0");
201	}
202#endif
203	set_km_env();
204	return 0;
205}
206EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
207
208static int fixed_sdram(void)
209{
210	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
211	u32 msize = 0;
212	u32 ddr_size;
213	u32 ddr_size_log2;
214
215	out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
216	out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
217	out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
218	out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
219	out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
220	out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
221	out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
222	out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
223	out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
224	out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
225	out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
226	out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
227	out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
228	udelay(200);
229	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
230
231	disable_addr_trans();
232	msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
233	enable_addr_trans();
234	msize /= (1024 * 1024);
235	if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
236		for (ddr_size = msize << 20, ddr_size_log2 = 0;
237			(ddr_size > 1);
238			ddr_size = ddr_size >> 1, ddr_size_log2++)
239			if (ddr_size & 1)
240				return -1;
241		out_be32(&im->sysconf.ddrlaw[0].ar,
242			(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
243		out_be32(&im->ddr.csbnds[0].csbnds,
244			(((msize / 16) - 1) & 0xff));
245	}
246
247	return msize;
248}
249
250int dram_init(void)
251{
252	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
253	u32 msize = 0;
254
255	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
256		return -ENXIO;
257
258	out_be32(&im->sysconf.ddrlaw[0].bar,
259		CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
260	msize = fixed_sdram();
261
262#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
263	/*
264	 * Initialize DDR ECC byte
265	 */
266	ddr_enable_ecc(msize * 1024 * 1024);
267#endif
268
269	/* return total bus SDRAM size(bytes)  -- DDR */
270	gd->ram_size = msize * 1024 * 1024;
271
272	return 0;
273}
274
275int checkboard(void)
276{
277	puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
278
279	if (piggy_present())
280		puts(" with PIGGY.");
281	puts("\n");
282	return 0;
283}
284
285int ft_board_setup(void *blob, struct bd_info *bd)
286{
287	ft_cpu_setup(blob, bd);
288
289	return 0;
290}
291
292#if defined(CONFIG_HUSH_INIT_VAR)
293int hush_init_var(void)
294{
295	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
296	return 0;
297}
298#endif
299
300#if defined(CONFIG_POST)
301int post_hotkeys_pressed(void)
302{
303	int testpin = 0;
304	struct km_bec_fpga *base =
305		(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
306	int testpin_reg = in_8(&base->CFG_TESTPIN_REG);
307	testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0;
308	debug("post_hotkeys_pressed: %d\n", !testpin);
309	return testpin;
310}
311
312ulong post_word_load(void)
313{
314	void* addr = (ulong *) (CPM_POST_WORD_ADDR);
315	debug("post_word_load 0x%08lX:  0x%08X\n", (ulong)addr, in_le32(addr));
316	return in_le32(addr);
317
318}
319void post_word_store(ulong value)
320{
321	void* addr = (ulong *) (CPM_POST_WORD_ADDR);
322	debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
323	out_le32(addr, value);
324}
325
326int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
327{
328	*vstart = CONFIG_SYS_MEMTEST_START;
329	*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
330	debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
331
332	return 0;
333}
334#endif
335