11556Srgrimes/* SPDX-License-Identifier: GPL-2.0+ */
21556Srgrimes/*
31556Srgrimes * Copyright 2004-2011 Freescale Semiconductor, Inc.
41556Srgrimes *
51556Srgrimes * MPC83xx Internal Memory Map
61556Srgrimes *
71556Srgrimes * Contributors:
81556Srgrimes *	Dave Liu <daveliu@freescale.com>
91556Srgrimes *	Tanya Jiang <tanya.jiang@freescale.com>
101556Srgrimes *	Mandy Lavi <mandy.lavi@freescale.com>
111556Srgrimes *	Eran Liberty <liberty@freescale.com>
121556Srgrimes */
131556Srgrimes#ifndef __IMMAP_83xx__
141556Srgrimes#define __IMMAP_83xx__
151556Srgrimes
161556Srgrimes#include <fsl_immap.h>
171556Srgrimes#include <asm/types.h>
181556Srgrimes#include <asm/fsl_i2c.h>
191556Srgrimes#include <asm/mpc8xxx_spi.h>
201556Srgrimes#include <asm/fsl_lbc.h>
211556Srgrimes#include <asm/fsl_dma.h>
221556Srgrimes
231556Srgrimes/*
241556Srgrimes * Local Access Window
251556Srgrimes */
261556Srgrimestypedef struct law83xx {
271556Srgrimes	u32 bar;		/* LBIU local access window base address register */
281556Srgrimes	u32 ar;			/* LBIU local access window attribute register */
291556Srgrimes} law83xx_t;
301556Srgrimes
311556Srgrimes/*
321556Srgrimes * System configuration registers
331556Srgrimes */
3436150Scharniertypedef struct sysconf83xx {
3536150Scharnier	u32 immrbar;		/* Internal memory map base address register */
3636150Scharnier	u8 res0[0x04];
371556Srgrimes	u32 altcbar;		/* Alternate configuration base address register */
3899110Sobrien	u8 res1[0x14];
3999110Sobrien	law83xx_t lblaw[4];	/* LBIU local access window */
401556Srgrimes	u8 res2[0x20];
4117987Speter	law83xx_t pcilaw[2];	/* PCI local access window */
4296922Stjr	u8 res3[0x10];
4317987Speter	law83xx_t pcielaw[2];	/* PCI Express local access window */
4417987Speter	u8 res4[0x10];
4517987Speter	law83xx_t ddrlaw[2];	/* DDR local access window */
4617987Speter	u8 res5[0x50];
4717987Speter	u32 sgprl;		/* System General Purpose Register Low */
4817987Speter	u32 sgprh;		/* System General Purpose Register High */
4917987Speter	u32 spridr;		/* System Part and Revision ID Register */
501556Srgrimes	u8 res6[0x04];
511556Srgrimes	u32 spcr;		/* System Priority Configuration Register */
521556Srgrimes	u32 sicrl;		/* System I/O Configuration Register Low */
531556Srgrimes	u32 sicrh;		/* System I/O Configuration Register High */
541556Srgrimes	u8 res7[0x04];
551556Srgrimes	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
561556Srgrimes	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
571556Srgrimes	u32 ddrcdr;		/* DDR Control Driver Register */
581556Srgrimes	u32 ddrdsr;		/* DDR Debug Status Register */
591556Srgrimes	u32 obir;		/* Output Buffer Impedance Register */
601556Srgrimes	u8 res8[0xC];
611556Srgrimes	u32 pecr1;		/* PCI Express control register 1 */
6296922Stjr#if defined(CONFIG_ARCH_MPC830X)
631556Srgrimes	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
641556Srgrimes#else
651556Srgrimes	u32 pecr2;		/* PCI Express control register 2 */
66199953Sjilles#endif
671556Srgrimes	u8 res9[0xB8];
681556Srgrimes} sysconf83xx_t;
691556Srgrimes
701556Srgrimes/*
711556Srgrimes * Watch Dog Timer (WDT) Registers
721556Srgrimes */
73100315Stjrtypedef struct wdt83xx {
741556Srgrimes	u8 res0[4];
751556Srgrimes	u32 swcrr;		/* System watchdog control register */
761556Srgrimes	u32 swcnr;		/* System watchdog count register */
771556Srgrimes	u8 res1[2];
781556Srgrimes	u16 swsrr;		/* System watchdog service register */
798855Srgrimes	u8 res2[0xF0];
801556Srgrimes} wdt83xx_t;
811556Srgrimes
828855Srgrimes/*
831556Srgrimes * RTC/PIT Module Registers
84213760Sobrien */
851556Srgrimestypedef struct rtclk83xx {
86213811Sobrien	u32 cnr;		/* control register */
87213811Sobrien	u32 ldr;		/* load register */
881556Srgrimes	u32 psr;		/* prescale register */
891556Srgrimes	u32 ctr;		/* counter value field register */
901556Srgrimes	u32 evr;		/* event register */
911556Srgrimes	u32 alr;		/* alarm register */
921556Srgrimes	u8 res0[0xE8];
931556Srgrimes} rtclk83xx_t;
941556Srgrimes
951556Srgrimes/*
96264629Sjilles * Global timer module
97264629Sjilles */
98264629Sjillestypedef struct gtm83xx {
99264629Sjilles	u8 cfr1;		/* Timer1/2 Configuration */
100264629Sjilles	u8 res0[3];
101264629Sjilles	u8 cfr2;		/* Timer3/4 Configuration */
102264629Sjilles	u8 res1[11];
1031556Srgrimes	u16 mdr1;		/* Timer1 Mode Register */
1041556Srgrimes	u16 mdr2;		/* Timer2 Mode Register */
1051556Srgrimes	u16 rfr1;		/* Timer1 Reference Register */
10690111Simp	u16 rfr2;		/* Timer2 Reference Register */
10790111Simp	u16 cpr1;		/* Timer1 Capture Register */
1081556Srgrimes	u16 cpr2;		/* Timer2 Capture Register */
10917987Speter	u16 cnr1;		/* Timer1 Counter Register */
1101556Srgrimes	u16 cnr2;		/* Timer2 Counter Register */
1111556Srgrimes	u16 mdr3;		/* Timer3 Mode Register */
11220425Ssteve	u16 mdr4;		/* Timer4 Mode Register */
1131556Srgrimes	u16 rfr3;		/* Timer3 Reference Register */
114264629Sjilles	u16 rfr4;		/* Timer4 Reference Register */
1151556Srgrimes	u16 cpr3;		/* Timer3 Capture Register */
1161556Srgrimes	u16 cpr4;		/* Timer4 Capture Register */
1171556Srgrimes	u16 cnr3;		/* Timer3 Counter Register */
1181556Srgrimes	u16 cnr4;		/* Timer4 Counter Register */
1191556Srgrimes	u16 evr1;		/* Timer1 Event Register */
1201556Srgrimes	u16 evr2;		/* Timer2 Event Register */
1211556Srgrimes	u16 evr3;		/* Timer3 Event Register */
1221556Srgrimes	u16 evr4;		/* Timer4 Event Register */
1231556Srgrimes	u16 psr1;		/* Timer1 Prescaler Register */
1241556Srgrimes	u16 psr2;		/* Timer2 Prescaler Register */
1251556Srgrimes	u16 psr3;		/* Timer3 Prescaler Register */
1261556Srgrimes	u16 psr4;		/* Timer4 Prescaler Register */
12711601Sjoerg	u8 res[0xC0];
12811601Sjoerg} gtm83xx_t;
12920425Ssteve
13025231Ssteve/*
1311556Srgrimes * Integrated Programmable Interrupt Controller
1321556Srgrimes */
13325231Sstevetypedef struct ipic83xx {
13425231Ssteve	u32 sicfr;		/* System Global Interrupt Configuration Register */
13525231Ssteve	u32 sivcr;		/* System Global Interrupt Vector Register */
136199953Sjilles	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
137199953Sjilles	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
13825231Ssteve	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
13925231Ssteve	u32 siprr_b;		/* System Internal Interrupt Group B Priority Register */
14025231Ssteve	u32 siprr_c;		/* System Internal Interrupt Group C Priority Register */
14125231Ssteve	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
14225231Ssteve	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
143199953Sjilles	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
144199953Sjilles	u32 sicnr;		/* System Internal Interrupt Control Register */
145199953Sjilles	u32 sepnr;		/* System External Interrupt Pending Register */
1461556Srgrimes	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
1471556Srgrimes	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
14825231Ssteve	u32 semsr;		/* System External Interrupt Mask Register */
14925231Ssteve	u32 secnr;		/* System External Interrupt Control Register */
150199953Sjilles	u32 sersr;		/* System Error Status Register */
151264629Sjilles	u32 sermr;		/* System Error Mask Register */
152264629Sjilles	u32 sercr;		/* System Error Control Register */
1531556Srgrimes	u32 sepcr;		/* System External Interrupt Polarity Control Register */
1541556Srgrimes	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
1551556Srgrimes	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
1561556Srgrimes	u32 sefcr;		/* System External Interrupt Force Register */
1571556Srgrimes	u32 serfr;		/* System Error Force Register */
158264629Sjilles	u32 scvcr;		/* System Critical Interrupt Vector Register */
1591556Srgrimes	u32 smvcr;		/* System Management Interrupt Vector Register */
1601556Srgrimes	u8 res[0x98];
1611556Srgrimes} ipic83xx_t;
162213811Sobrien
16390111Simp/*
16490111Simp * System Arbiter Registers
16596922Stjr */
1661556Srgrimestypedef struct arbiter83xx {
1671556Srgrimes	u32 acr;		/* Arbiter Configuration Register */
1681556Srgrimes	u32 atr;		/* Arbiter Timers Register */
169216851Sjilles	u8 res[4];
1701556Srgrimes	u32 aer;		/* Arbiter Event Register */
1711556Srgrimes	u32 aidr;		/* Arbiter Interrupt Definition Register */
1721556Srgrimes	u32 amr;		/* Arbiter Mask Register */
1731556Srgrimes	u32 aeatr;		/* Arbiter Event Attributes Register */
1741556Srgrimes	u32 aeadr;		/* Arbiter Event Address Register */
1751556Srgrimes	u32 aerr;		/* Arbiter Event Response Register */
176104132Stjr	u8 res1[0xDC];
1771556Srgrimes} arbiter83xx_t;
1781556Srgrimes
179216851Sjilles/*
180216851Sjilles * Reset Module
181216851Sjilles */
182216851Sjillestypedef struct reset83xx {
183216851Sjilles	u32 rcwl;		/* Reset Configuration Word Low Register */
1841556Srgrimes	u32 rcwh;		/* Reset Configuration Word High Register */
1851556Srgrimes	u8 res0[8];
1861556Srgrimes	u32 rsr;		/* Reset Status Register */
18766612Sbrian	u32 rmr;		/* Reset Mode Register */
18866612Sbrian	u32 rpr;		/* Reset protection Register */
18966612Sbrian	u32 rcr;		/* Reset Control Register */
190104132Stjr	u32 rcer;		/* Reset Control Enable Register */
19166612Sbrian	u8 res1[0xDC];
1921556Srgrimes} reset83xx_t;
193194560Sjilles
194194560Sjilles/*
195194560Sjilles * Clock Module
196194560Sjilles */
197194560Sjillestypedef struct clk83xx {
198194560Sjilles	u32 spmr;		/* system PLL mode Register */
199194560Sjilles	u32 occr;		/* output clock control Register */
200194560Sjilles	u32 sccr;		/* system clock control Register */
201194560Sjilles	u8 res0[0xF4];
202194560Sjilles} clk83xx_t;
203194560Sjilles
204194560Sjilles/*
205194560Sjilles * Power Management Control Module
206194560Sjilles */
207194560Sjillestypedef struct pmc83xx {
208194560Sjilles	u32 pmccr;		/* PMC Configuration Register */
209194560Sjilles	u32 pmcer;		/* PMC Event Register */
210194560Sjilles	u32 pmcmr;		/* PMC Mask Register */
211194560Sjilles	u32 pmccr1;		/* PMC Configuration Register 1 */
21296922Stjr	u32 pmccr2;		/* PMC Configuration Register 2 */
21396922Stjr	u8 res0[0xEC];
21496922Stjr} pmc83xx_t;
215104132Stjr
21696922Stjr/*
2171556Srgrimes * General purpose I/O module
2181556Srgrimes */
2191556Srgrimestypedef struct gpio83xx {
220104132Stjr	u32 dir;		/* direction register */
2211556Srgrimes	u32 odr;		/* open drain register */
2221556Srgrimes	u32 dat;		/* data register */
2231556Srgrimes	u32 ier;		/* interrupt event register */
2241556Srgrimes	u32 imr;		/* interrupt mask register */
2251556Srgrimes	u32 icr;		/* external interrupt control register */
2261556Srgrimes	u8 res0[0xE8];
227214290Sjilles} gpio83xx_t;
228214290Sjilles
229214290Sjilles/*
230214290Sjilles * QE Ports Interrupts Registers
231214290Sjilles */
232124780Sdestypedef struct qepi83xx {
23399645Stjr	u8 res0[0xC];
234124780Sdes	u32 qepier;		/* QE Ports Interrupt Event Register */
2351556Srgrimes	u32 qepimr;		/* QE Ports Interrupt Mask Register */
2361556Srgrimes	u32 qepicr;		/* QE Ports Interrupt Control Register */
2371556Srgrimes	u8 res1[0xE8];
2381556Srgrimes} qepi83xx_t;
2391556Srgrimes
2401556Srgrimes/*
2411556Srgrimes * QE Parallel I/O Ports
2421556Srgrimes */
2431556Srgrimestypedef struct gpio_n {
2441556Srgrimes	u32 podr;		/* Open Drain Register */
2451556Srgrimes	u32 pdat;		/* Data Register */
2461556Srgrimes	u32 dir1;		/* direction register 1 */
2471556Srgrimes	u32 dir2;		/* direction register 2 */
2481556Srgrimes	u32 ppar1;		/* Pin Assignment Register 1 */
2491556Srgrimes	u32 ppar2;		/* Pin Assignment Register 2 */
2501556Srgrimes} gpio_n_t;
2511556Srgrimes
252213811Sobrientypedef struct qegpio83xx {
25390111Simp	gpio_n_t ioport[0x7];
25490111Simp	u8 res0[0x358];
2551556Srgrimes} qepio83xx_t;
25617987Speter
2571556Srgrimes/*
2581556Srgrimes * QE Secondary Bus Access Windows
25953891Scracauer */
2601556Srgrimestypedef struct qesba83xx {
2611556Srgrimes	u32 lbmcsar;		/* Local bus memory controller start address */
2621556Srgrimes	u32 sdmcsar;		/* Secondary DDR memory controller start address */
2631556Srgrimes	u8 res0[0x38];
2641556Srgrimes	u32 lbmcear;		/* Local bus memory controller end address */
2651556Srgrimes	u32 sdmcear;		/* Secondary DDR memory controller end address */
2661556Srgrimes	u8 res1[0x38];
2671556Srgrimes	u32 lbmcar;		/* Local bus memory controller attributes */
2681556Srgrimes	u32 sdmcar;		/* Secondary DDR memory controller attributes */
2691556Srgrimes	u8 res2[0x378];
2701556Srgrimes} qesba83xx_t;
2711556Srgrimes
2721556Srgrimes/*
2731556Srgrimes * DDR Memory Controller Memory Map for DDR1
2741556Srgrimes * The structure of DDR2, or DDR3 is defined in fsl_immap.h
2751556Srgrimes */
2761556Srgrimes#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
2771556Srgrimestypedef struct ddr_cs_bnds {
2781556Srgrimes	u32 csbnds;
2791556Srgrimes	u8 res0[4];
2801556Srgrimes} ddr_cs_bnds_t;
2811556Srgrimes
2821556Srgrimestypedef struct ddr83xx {
2831556Srgrimes	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
2841556Srgrimes	u8 res0[0x60];
2851556Srgrimes	u32 cs_config[4];	/* Chip Select x Configuration */
2861556Srgrimes	u8 res1[0x70];
2871556Srgrimes	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
2881556Srgrimes	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
2891556Srgrimes	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
2901556Srgrimes	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
2911556Srgrimes	u32 sdram_cfg;		/* SDRAM Control Configuration */
29290111Simp	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
29390111Simp	u32 sdram_mode;		/* SDRAM Mode Configuration */
29425231Ssteve	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
2951556Srgrimes	u32 sdram_md_cntl;	/* SDRAM Mode Control */
2961556Srgrimes	u32 sdram_interval;	/* SDRAM Interval Configuration */
2971556Srgrimes	u32 ddr_data_init;	/* SDRAM Data Initialization */
2981556Srgrimes	u8 res2[4];
2991556Srgrimes	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
3001556Srgrimes	u8 res3[0x14];
3011556Srgrimes	u32 ddr_init_addr;	/* DDR training initialization address */
302124780Sdes	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
3031556Srgrimes	u8 res4[0xAA8];
304124780Sdes	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
305124780Sdes	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
3061556Srgrimes	u8 res5[0x200];
3071556Srgrimes	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
3081556Srgrimes	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
3091556Srgrimes	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
3101556Srgrimes	u8 res6[0x14];
3111556Srgrimes	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
3121556Srgrimes	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
3131556Srgrimes	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
3141556Srgrimes	u8 res7[0x14];
3151556Srgrimes	u32 err_detect;		/* Memory Error Detect */
3161556Srgrimes	u32 err_disable;	/* Memory Error Disable */
3171556Srgrimes	u32 err_int_en;		/* Memory Error Interrupt Enable */
3181556Srgrimes	u32 capture_attributes;	/* Memory Error Attributes Capture */
3191556Srgrimes	u32 capture_address;	/* Memory Error Address Capture */
3201556Srgrimes	u32 capture_ext_address;/* Memory Error Extended Address Capture */
3211556Srgrimes	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
3221556Srgrimes	u8 res8[0xA4];
3231556Srgrimes	u32 debug_reg;
3241556Srgrimes	u8 res9[0xFC];
3251556Srgrimes} ddr83xx_t;
3261556Srgrimes#endif
3271556Srgrimes
3281556Srgrimes/*
3291556Srgrimes * DUART
3301556Srgrimes */
3311556Srgrimestypedef struct duart83xx {
33290111Simp	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
33390111Simp	u8 uier_udmb;		/* combined register for UIER and UDMB */
3341556Srgrimes	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
3351556Srgrimes	u8 ulcr;		/* line control register */
3361556Srgrimes	u8 umcr;		/* MODEM control register */
3371556Srgrimes	u8 ulsr;		/* line status register */
3381556Srgrimes	u8 umsr;		/* MODEM status register */
3391556Srgrimes	u8 uscr;		/* scratch register */
3401556Srgrimes	u8 res0[8];
3411556Srgrimes	u8 udsr;		/* DMA status register */
34290111Simp	u8 res1[3];
34390111Simp	u8 res2[0xEC];
34425231Ssteve} duart83xx_t;
3451556Srgrimes
3461556Srgrimes/*
3471556Srgrimes * DMA/Messaging Unit
3481556Srgrimes */
3491556Srgrimestypedef struct dma83xx {
3501556Srgrimes	u32 res0[0xC];		/* 0x0-0x29 reseverd */
3511556Srgrimes	u32 omisr;		/* 0x30 Outbound message interrupt status register */
3521556Srgrimes	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
3531556Srgrimes	u32 res1[0x6];		/* 0x38-0x49 reserved */
3541556Srgrimes	u32 imr0;		/* 0x50 Inbound message register 0 */
3551556Srgrimes	u32 imr1;		/* 0x54 Inbound message register 1 */
356	u32 omr0;		/* 0x58 Outbound message register 0 */
357	u32 omr1;		/* 0x5C Outbound message register 1 */
358	u32 odr;		/* 0x60 Outbound doorbell register */
359	u32 res2;		/* 0x64-0x67 reserved */
360	u32 idr;		/* 0x68 Inbound doorbell register */
361	u32 res3[0x5];		/* 0x6C-0x79 reserved */
362	u32 imisr;		/* 0x80 Inbound message interrupt status register */
363	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
364	u32 res4[0x1E];		/* 0x88-0x99 reserved */
365	struct fsl_dma dma[4];
366} dma83xx_t;
367
368/*
369 * PCI Software Configuration Registers
370 */
371typedef struct pciconf83xx {
372	u32 config_address;
373	u32 config_data;
374	u32 int_ack;
375	u8 res[116];
376} pciconf83xx_t;
377
378/*
379 * PCI Outbound Translation Register
380 */
381typedef struct pci_outbound_window {
382	u32 potar;
383	u8 res0[4];
384	u32 pobar;
385	u8 res1[4];
386	u32 pocmr;
387	u8 res2[4];
388} pot83xx_t;
389
390/*
391 * Sequencer
392 */
393typedef struct ios83xx {
394	pot83xx_t pot[6];
395	u8 res0[0x60];
396	u32 pmcr;
397	u8 res1[4];
398	u32 dtcr;
399	u8 res2[4];
400} ios83xx_t;
401
402/*
403 * PCI Controller Control and Status Registers
404 */
405typedef struct pcictrl83xx {
406	u32 esr;
407	u32 ecdr;
408	u32 eer;
409	u32 eatcr;
410	u32 eacr;
411	u32 eeacr;
412	u32 edlcr;
413	u32 edhcr;
414	u32 gcr;
415	u32 ecr;
416	u32 gsr;
417	u8 res0[12];
418	u32 pitar2;
419	u8 res1[4];
420	u32 pibar2;
421	u32 piebar2;
422	u32 piwar2;
423	u8 res2[4];
424	u32 pitar1;
425	u8 res3[4];
426	u32 pibar1;
427	u32 piebar1;
428	u32 piwar1;
429	u8 res4[4];
430	u32 pitar0;
431	u8 res5[4];
432	u32 pibar0;
433	u8 res6[4];
434	u32 piwar0;
435	u8 res7[132];
436} pcictrl83xx_t;
437
438/*
439 * USB
440 */
441typedef struct usb83xx {
442	u8 fixme[0x1000];
443} usb83xx_t;
444
445/*
446 * TSEC
447 */
448typedef struct tsec83xx {
449	u8 fixme[0x1000];
450} tsec83xx_t;
451
452/*
453 * Security
454 */
455typedef struct security83xx {
456	u8 fixme[0x10000];
457} security83xx_t;
458
459/*
460 *  PCI Express
461 */
462struct pex_inbound_window {
463	u32 ar;
464	u32 tar;
465	u32 barl;
466	u32 barh;
467};
468
469struct pex_outbound_window {
470	u32 ar;
471	u32 bar;
472	u32 tarl;
473	u32 tarh;
474};
475
476struct pex_csb_bridge {
477	u32 pex_csb_ver;
478	u32 pex_csb_cab;
479	u32 pex_csb_ctrl;
480	u8 res0[8];
481	u32 pex_dms_dstmr;
482	u8 res1[4];
483	u32 pex_cbs_stat;
484	u8 res2[0x20];
485	u32 pex_csb_obctrl;
486	u32 pex_csb_obstat;
487	u8 res3[0x98];
488	u32 pex_csb_ibctrl;
489	u32 pex_csb_ibstat;
490	u8 res4[0xb8];
491	u32 pex_wdma_ctrl;
492	u32 pex_wdma_addr;
493	u32 pex_wdma_stat;
494	u8 res5[0x94];
495	u32 pex_rdma_ctrl;
496	u32 pex_rdma_addr;
497	u32 pex_rdma_stat;
498	u8 res6[0xd4];
499	u32 pex_ombcr;
500	u32 pex_ombdr;
501	u8 res7[0x38];
502	u32 pex_imbcr;
503	u32 pex_imbdr;
504	u8 res8[0x38];
505	u32 pex_int_enb;
506	u32 pex_int_stat;
507	u32 pex_int_apio_vec1;
508	u32 pex_int_apio_vec2;
509	u8 res9[0x10];
510	u32 pex_int_ppio_vec1;
511	u32 pex_int_ppio_vec2;
512	u32 pex_int_wdma_vec1;
513	u32 pex_int_wdma_vec2;
514	u32 pex_int_rdma_vec1;
515	u32 pex_int_rdma_vec2;
516	u32 pex_int_misc_vec;
517	u8 res10[4];
518	u32 pex_int_axi_pio_enb;
519	u32 pex_int_axi_wdma_enb;
520	u32 pex_int_axi_rdma_enb;
521	u32 pex_int_axi_misc_enb;
522	u32 pex_int_axi_pio_stat;
523	u32 pex_int_axi_wdma_stat;
524	u32 pex_int_axi_rdma_stat;
525	u32 pex_int_axi_misc_stat;
526	u8 res11[0xa0];
527	struct pex_outbound_window pex_outbound_win[4];
528	u8 res12[0x100];
529	u32 pex_epiwtar0;
530	u32 pex_epiwtar1;
531	u32 pex_epiwtar2;
532	u32 pex_epiwtar3;
533	u8 res13[0x70];
534	struct pex_inbound_window pex_inbound_win[4];
535};
536
537typedef struct pex83xx {
538	u8 pex_cfg_header[0x404];
539	u32 pex_ltssm_stat;
540	u8 res0[0x30];
541	u32 pex_ack_replay_timeout;
542	u8 res1[4];
543	u32 pex_gclk_ratio;
544	u8 res2[0xc];
545	u32 pex_pm_timer;
546	u32 pex_pme_timeout;
547	u8 res3[4];
548	u32 pex_aspm_req_timer;
549	u8 res4[0x18];
550	u32 pex_ssvid_update;
551	u8 res5[0x34];
552	u32 pex_cfg_ready;
553	u8 res6[0x24];
554	u32 pex_bar_sizel;
555	u8 res7[4];
556	u32 pex_bar_sel;
557	u8 res8[0x20];
558	u32 pex_bar_pf;
559	u8 res9[0x88];
560	u32 pex_pme_to_ack_tor;
561	u8 res10[0xc];
562	u32 pex_ss_intr_mask;
563	u8 res11[0x25c];
564	struct pex_csb_bridge bridge;
565	u8 res12[0x160];
566} pex83xx_t;
567
568/*
569 * SATA
570 */
571typedef struct sata83xx {
572	u8 fixme[0x1000];
573} sata83xx_t;
574
575/*
576 * eSDHC
577 */
578typedef struct sdhc83xx {
579	u8 fixme[0x1000];
580} sdhc83xx_t;
581
582/*
583 * SerDes
584 */
585typedef struct serdes83xx {
586	u32 srdscr0;
587	u32 srdscr1;
588	u32 srdscr2;
589	u32 srdscr3;
590	u32 srdscr4;
591	u8 res0[0xc];
592	u32 srdsrstctl;
593	u8 res1[0xdc];
594} serdes83xx_t;
595
596/*
597 * On Chip ROM
598 */
599typedef struct rom83xx {
600	u8 mem[0x10000];
601} rom83xx_t;
602
603/*
604 * TDM
605 */
606typedef struct tdm83xx {
607	u8 fixme[0x200];
608} tdm83xx_t;
609
610/*
611 * TDM DMAC
612 */
613typedef struct tdmdmac83xx {
614	u8 fixme[0x2000];
615} tdmdmac83xx_t;
616
617#if defined(CONFIG_ARCH_MPC834X)
618typedef struct immap {
619	sysconf83xx_t		sysconf;	/* System configuration */
620	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
621	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
622	rtclk83xx_t		pit;		/* Periodic Interval Timer */
623	gtm83xx_t		gtm[2];		/* Global Timers Module */
624	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
625	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
626	reset83xx_t		reset;		/* Reset Module */
627	clk83xx_t		clk;		/* System Clock Module */
628	pmc83xx_t		pmc;		/* Power Management Control Module */
629	gpio83xx_t		gpio[2];	/* General purpose I/O module */
630	u8			res0[0x200];
631	u8			dll_ddr[0x100];
632	u8			dll_lbc[0x100];
633	u8			res1[0xE00];
634#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
635	struct ccsr_ddr		ddr;	/* DDR Memory Controller Memory */
636#else
637	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
638#endif
639	fsl_i2c_t		i2c[2];		/* I2C Controllers */
640	u8			res2[0x1300];
641	duart83xx_t		duart[2];	/* DUART */
642	u8			res3[0x900];
643	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
644	u8			res4[0x1000];
645	spi8xxx_t		spi;		/* Serial Peripheral Interface */
646	dma83xx_t		dma;		/* DMA */
647	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
648	ios83xx_t		ios;		/* Sequencer */
649	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
650	u8			res5[0x19900];
651	usb83xx_t		usb[2];
652	tsec83xx_t		tsec[2];
653	u8			res6[0xA000];
654	security83xx_t		security;
655	u8			res7[0xC0000];
656} immap_t;
657
658#elif defined(CONFIG_ARCH_MPC8313)
659typedef struct immap {
660	sysconf83xx_t		sysconf;	/* System configuration */
661	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
662	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
663	rtclk83xx_t		pit;		/* Periodic Interval Timer */
664	gtm83xx_t		gtm[2];		/* Global Timers Module */
665	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
666	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
667	reset83xx_t		reset;		/* Reset Module */
668	clk83xx_t		clk;		/* System Clock Module */
669	pmc83xx_t		pmc;		/* Power Management Control Module */
670	gpio83xx_t		gpio[1];	/* General purpose I/O module */
671	u8			res0[0x1300];
672	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
673	fsl_i2c_t		i2c[2];		/* I2C Controllers */
674	u8			res1[0x1300];
675	duart83xx_t		duart[2];	/* DUART */
676	u8			res2[0x900];
677	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
678	u8			res3[0x1000];
679	spi8xxx_t		spi;		/* Serial Peripheral Interface */
680	dma83xx_t		dma;		/* DMA */
681	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
682	u8			res4[0x80];
683	ios83xx_t		ios;		/* Sequencer */
684	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
685	u8			res5[0x1aa00];
686	usb83xx_t		usb[1];
687	tsec83xx_t		tsec[2];
688	u8			res6[0xA000];
689	security83xx_t		security;
690	u8			res7[0xC0000];
691} immap_t;
692
693#elif defined(CONFIG_ARCH_MPC8308)
694typedef struct immap {
695	sysconf83xx_t		sysconf;	/* System configuration */
696	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
697	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
698	rtclk83xx_t		pit;		/* Periodic Interval Timer */
699	gtm83xx_t		gtm[1];		/* Global Timers Module */
700	u8			res0[0x100];
701	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
702	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
703	reset83xx_t		reset;		/* Reset Module */
704	clk83xx_t		clk;		/* System Clock Module */
705	pmc83xx_t		pmc;		/* Power Management Control Module */
706	gpio83xx_t		gpio[1];	/* General purpose I/O module */
707	u8			res1[0x1300];
708	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
709	fsl_i2c_t		i2c[2];		/* I2C Controllers */
710	u8			res2[0x1300];
711	duart83xx_t		duart[2];	/* DUART */
712	u8			res3[0x900];
713	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
714	u8			res4[0x1000];
715	spi8xxx_t		spi;		/* Serial Peripheral Interface */
716	u8			res5[0x1000];
717	pex83xx_t		pciexp[1];	/* PCI Express Controller */
718	u8			res6[0x19000];
719	usb83xx_t		usb[1];		/* USB DR Controller */
720	tsec83xx_t		tsec[2];
721	u8			res7[0x6000];
722	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
723	sdhc83xx_t		sdhc;		/* SDHC Controller */
724	u8			res8[0xb4000];
725	serdes83xx_t		serdes[1];	/* SerDes Registers */
726	u8			res9[0x1CF00];
727} immap_t;
728
729#elif defined(CONFIG_ARCH_MPC837X)
730typedef struct immap {
731	sysconf83xx_t		sysconf;	/* System configuration */
732	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
733	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
734	rtclk83xx_t		pit;		/* Periodic Interval Timer */
735	gtm83xx_t		gtm[2];		/* Global Timers Module */
736	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
737	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
738	reset83xx_t		reset;		/* Reset Module */
739	clk83xx_t		clk;		/* System Clock Module */
740	pmc83xx_t		pmc;		/* Power Management Control Module */
741	gpio83xx_t		gpio[2];	/* General purpose I/O module */
742	u8			res0[0x1200];
743	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
744	fsl_i2c_t		i2c[2];		/* I2C Controllers */
745	u8			res1[0x1300];
746	duart83xx_t		duart[2];	/* DUART */
747	u8			res2[0x900];
748	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
749	u8			res3[0x1000];
750	spi8xxx_t		spi;		/* Serial Peripheral Interface */
751	dma83xx_t		dma;		/* DMA */
752	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
753	u8			res4[0x80];
754	ios83xx_t		ios;		/* Sequencer */
755	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
756	u8			res5[0xa00];
757	pex83xx_t		pciexp[2];	/* PCI Express Controller */
758	u8			res6[0xd000];
759	sata83xx_t		sata[4];	/* SATA Controller */
760	u8			res7[0x7000];
761	usb83xx_t		usb[1];		/* USB DR Controller */
762	tsec83xx_t		tsec[2];
763	u8			res8[0x8000];
764	sdhc83xx_t		sdhc;		/* SDHC Controller */
765	u8			res9[0x1000];
766	security83xx_t		security;
767	u8			res10[0xA3000];
768	serdes83xx_t		serdes[2];	/* SerDes Registers */
769	u8			res11[0xCE00];
770	rom83xx_t		rom;		/* On Chip ROM */
771} immap_t;
772
773#elif defined(CONFIG_ARCH_MPC8360)
774typedef struct immap {
775	sysconf83xx_t		sysconf;	/* System configuration */
776	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
777	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
778	rtclk83xx_t		pit;		/* Periodic Interval Timer */
779	u8			res0[0x200];
780	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
781	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
782	reset83xx_t		reset;		/* Reset Module */
783	clk83xx_t		clk;		/* System Clock Module */
784	pmc83xx_t		pmc;		/* Power Management Control Module */
785	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
786	u8			res1[0x300];
787	u8			dll_ddr[0x100];
788	u8			dll_lbc[0x100];
789	u8			res2[0x200];
790	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
791	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
792	u8			res3[0x400];
793	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
794	fsl_i2c_t		i2c[2];		/* I2C Controllers */
795	u8			res4[0x1300];
796	duart83xx_t		duart[2];	/* DUART */
797	u8			res5[0x900];
798	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
799	u8			res6[0x2000];
800	dma83xx_t		dma;		/* DMA */
801	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
802	u8			res7[128];
803	ios83xx_t		ios;		/* Sequencer (IOS) */
804	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
805	u8			res8[0x4A00];
806	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
807	u8			res9[0x22000];
808	security83xx_t		security;
809	u8			res10[0xC0000];
810	u8			qe[0x100000];	/* QE block */
811} immap_t;
812
813#elif defined(CONFIG_ARCH_MPC832X)
814typedef struct immap {
815	sysconf83xx_t		sysconf;	/* System configuration */
816	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
817	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
818	rtclk83xx_t		pit;		/* Periodic Interval Timer */
819	gtm83xx_t		gtm[2];		/* Global Timers Module */
820	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
821	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
822	reset83xx_t		reset;		/* Reset Module */
823	clk83xx_t		clk;		/* System Clock Module */
824	pmc83xx_t		pmc;		/* Power Management Control Module */
825	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
826	u8			res0[0x300];
827	u8			dll_ddr[0x100];
828	u8			dll_lbc[0x100];
829	u8			res1[0x200];
830	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
831	u8			res2[0x800];
832	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
833	fsl_i2c_t		i2c[2];		/* I2C Controllers */
834	u8			res3[0x1300];
835	duart83xx_t		duart[2];	/* DUART */
836	u8			res4[0x900];
837	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
838	u8			res5[0x2000];
839	dma83xx_t		dma;		/* DMA */
840	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
841	u8			res6[128];
842	ios83xx_t		ios;		/* Sequencer (IOS) */
843	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
844	u8			res7[0x27A00];
845	security83xx_t		security;
846	u8			res8[0xC0000];
847	u8			qe[0x100000];	/* QE block */
848} immap_t;
849#endif
850
851struct ccsr_gpio {
852	u32	gpdir;
853	u32	gpodr;
854	u32	gpdat;
855	u32	gpier;
856	u32	gpimr;
857	u32	gpicr;
858	union	{
859			u32	gpibe;
860			u8	res0[0xE8];
861	};
862};
863
864#define CFG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
865#define CFG_SYS_FSL_DDR_ADDR \
866			(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
867#define CFG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
868#define CFG_SYS_MPC83xx_DMA_ADDR \
869			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
870#define CFG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
871#define CFG_SYS_MPC83xx_ESDHC_ADDR \
872			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
873
874#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
875
876#endif				/* __IMMAP_83xx__ */
877