1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Derived from mpc85xx_ddr_gen3.c, removed all workarounds 6 */ 7 8#include <common.h> 9#include <log.h> 10#include <asm/io.h> 11#include <fsl_ddr_sdram.h> 12#include <asm/processor.h> 13#include <fsl_immap.h> 14#include <fsl_ddr.h> 15#include <asm/arch/clock.h> 16#include <linux/delay.h> 17 18#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) 19#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL 20#endif 21 22 23/* 24 * regs has the to-be-set values for DDR controller registers 25 * ctrl_num is the DDR controller number 26 * step: 0 goes through the initialization in one pass 27 * 1 sets registers and returns before enabling controller 28 * 2 resumes from step 1 and continues to initialize 29 * Dividing the initialization to two steps to deassert DDR reset signal 30 * to comply with JEDEC specs for RDIMMs. 31 */ 32void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, 33 unsigned int ctrl_num, int step) 34{ 35 unsigned int i, bus_width; 36 struct ccsr_ddr __iomem *ddr; 37 u32 temp_sdram_cfg; 38 u32 total_gb_size_per_controller; 39 int timeout; 40 41 switch (ctrl_num) { 42 case 0: 43 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; 44 break; 45#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 46 case 1: 47 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; 48 break; 49#endif 50#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 51 case 2: 52 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; 53 break; 54#endif 55#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 56 case 3: 57 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 58 break; 59#endif 60 default: 61 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 62 return; 63 } 64 65 if (step == 2) 66 goto step2; 67 68 if (regs->ddr_eor) 69 ddr_out32(&ddr->eor, regs->ddr_eor); 70 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 71 if (i == 0) { 72 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); 73 ddr_out32(&ddr->cs0_config, regs->cs[i].config); 74 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); 75 76 } else if (i == 1) { 77 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); 78 ddr_out32(&ddr->cs1_config, regs->cs[i].config); 79 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); 80 81 } else if (i == 2) { 82 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); 83 ddr_out32(&ddr->cs2_config, regs->cs[i].config); 84 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); 85 86 } else if (i == 3) { 87 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); 88 ddr_out32(&ddr->cs3_config, regs->cs[i].config); 89 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); 90 } 91 } 92 93 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); 94 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); 95 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); 96 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); 97 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); 98 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); 99 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); 100 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); 101 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); 102 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); 103 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); 104 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); 105 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); 106 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); 107 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); 108 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); 109 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); 110 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); 111 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); 112 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); 113#ifndef CONFIG_SYS_FSL_DDR_EMU 114 /* 115 * Skip these two registers if running on emulator 116 * because emulator doesn't have skew between bytes. 117 */ 118 119 if (regs->ddr_wrlvl_cntl_2) 120 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); 121 if (regs->ddr_wrlvl_cntl_3) 122 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); 123#endif 124 125 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); 126 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); 127 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); 128 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); 129#ifdef CONFIG_DEEP_SLEEP 130 if (is_warm_boot()) { 131 ddr_out32(&ddr->sdram_cfg_2, 132 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 133 ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); 134 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); 135 136 /* DRAM VRef will not be trained */ 137 ddr_out32(&ddr->ddr_cdr2, 138 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); 139 } else 140#endif 141 { 142 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 143 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); 144 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); 145 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); 146 } 147 ddr_out32(&ddr->err_disable, regs->err_disable); 148 ddr_out32(&ddr->err_int_en, regs->err_int_en); 149 for (i = 0; i < 32; i++) { 150 if (regs->debug[i]) { 151 debug("Write to debug_%d as %08x\n", i + 1, 152 regs->debug[i]); 153 ddr_out32(&ddr->debug[i], regs->debug[i]); 154 } 155 } 156 157 /* 158 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is 159 * deasserted. Clocks start when any chip select is enabled and clock 160 * control register is set. Because all DDR components are connected to 161 * one reset signal, this needs to be done in two steps. Step 1 is to 162 * get the clocks started. Step 2 resumes after reset signal is 163 * deasserted. 164 */ 165 if (step == 1) { 166 udelay(200); 167 return; 168 } 169 170step2: 171 /* Set, but do not enable the memory */ 172 temp_sdram_cfg = regs->ddr_sdram_cfg; 173 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); 174 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); 175 176 /* 177 * 500 painful micro-seconds must elapse between 178 * the DDR clock setup and the DDR config enable. 179 * DDR2 need 200 us, and DDR3 need 500 us from spec, 180 * we choose the max, that is 500 us for all of case. 181 */ 182 udelay(500); 183 asm volatile("dsb sy;isb"); 184 185#ifdef CONFIG_DEEP_SLEEP 186 if (is_warm_boot()) { 187 /* enter self-refresh */ 188 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 189 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; 190 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 191 /* do board specific memory setup */ 192 board_mem_sleep_setup(); 193 194 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); 195 } else 196#endif 197 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; 198 /* Let the controller go */ 199 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); 200 asm volatile("dsb sy;isb"); 201 202 total_gb_size_per_controller = 0; 203 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 204 if (!(regs->cs[i].config & 0x80000000)) 205 continue; 206 total_gb_size_per_controller += 1 << ( 207 ((regs->cs[i].config >> 14) & 0x3) + 2 + 208 ((regs->cs[i].config >> 8) & 0x7) + 12 + 209 ((regs->cs[i].config >> 0) & 0x7) + 8 + 210 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - 211 26); /* minus 26 (count of 64M) */ 212 } 213 if (regs->cs[0].config & 0x20000000) { 214 /* 2-way interleaving */ 215 total_gb_size_per_controller <<= 1; 216 } 217 /* 218 * total memory / bus width = transactions needed 219 * transactions needed / data rate = seconds 220 * to add plenty of buffer, double the time 221 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms 222 * Let's wait for 800ms 223 */ 224 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) 225 >> SDRAM_CFG_DBW_SHIFT); 226 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / 227 (get_ddr_freq(ctrl_num) >> 20)) << 1; 228 total_gb_size_per_controller >>= 4; /* shift down to gb size */ 229 debug("total %d GB\n", total_gb_size_per_controller); 230 debug("Need to wait up to %d * 10ms\n", timeout); 231 232 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 233 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && 234 (timeout >= 0)) { 235 udelay(10000); /* throttle polling rate */ 236 timeout--; 237 } 238 239 if (timeout <= 0) 240 printf("Waiting for D_INIT timeout. Memory may not work.\n"); 241#ifdef CONFIG_DEEP_SLEEP 242 if (is_warm_boot()) { 243 /* exit self-refresh */ 244 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); 245 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; 246 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); 247 } 248#endif 249} 250