| /u-boot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen1.c | 47 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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| H A D | mpc85xx_ddr_gen2.c | 69 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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| H A D | arm_ddr_gen3.c | 95 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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| H A D | util.c | 243 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
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| H A D | fsl_ddr_gen4.c | 171 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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| H A D | mpc85xx_ddr_gen3.c | 127 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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| H A D | ctrl_regs.c | 621 ddr->timing_cfg_1 = (0
631 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
1936 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
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| H A D | interactive.c | 634 CFG_REGS(timing_cfg_1),
725 CFG_REGS(timing_cfg_1),
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| /u-boot/board/socrates/ |
| H A D | sdram.c | 40 ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
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| /u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.h | 61 .timing_cfg_1 = 0xBBB48C42,
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| /u-boot/board/gdsys/mpc8308/ |
| H A D | sdram.c | 53 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
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| /u-boot/board/kontron/sl28/ |
| H A D | ddr.c | 29 .timing_cfg_1 = 0xbcb48c66,
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| /u-boot/board/freescale/ls1021atsn/ |
| H A D | ls1021atsn.c | 40 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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| /u-boot/board/freescale/ls1021aiot/ |
| H A D | ls1021aiot.c | 64 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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| /u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 332 u32 timing_cfg_1; local
678 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
690 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
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| /u-boot/board/freescale/mpc837xerdb/ |
| H A D | mpc837xerdb.c | 117 im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 222 .timing_cfg_1 = CFG_SYS_DDR_TIMING_1,
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| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 219 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
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| /u-boot/include/ |
| H A D | fsl_immap.h | 35 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ member in struct:ccsr_ddr
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| H A D | fsl_ddr_sdram.h | 250 unsigned int timing_cfg_1; member in struct:fsl_ddr_cfg_regs_s
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| H A D | spd_sdram.c | 538 ddr->timing_cfg_1 =
640 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
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| /u-boot/board/cssi/cmpcpro/ |
| H A D | cmpcpro.c | 309 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
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| /u-boot/board/freescale/ls1021atwr/ |
| H A D | ls1021atwr.c | 155 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 289 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ member in struct:ddr83xx
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