Searched refs:IFX_REG_W32 (Results 1 - 14 of 14) sorted by relevance

/openwrt/package/kernel/lantiq/ltq-ptm/src/
H A Difxmips_ptm_vr9.c102 IFX_REG_W32(0x00000001, PDMA_CFG);
103 IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);
104 IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);
105 IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);
106 IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);
108 IFX_REG_W32(0x00000011, SAR_MODE_CFG);
109 IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);
110 IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);
111 IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);
112 IFX_REG_W32(
[all...]
H A Difxmips_ptm_amazon_se.c164 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
165 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
166 IFX_REG_W32(0x000000FF, EMA_IER);
167 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
172 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
173 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
174 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
175 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
180 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
181 IFX_REG_W32(
[all...]
H A Difxmips_ptm_danube.c159 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
160 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
161 IFX_REG_W32(0x000000FF, EMA_IER);
162 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
167 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
168 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
169 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
170 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
175 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
176 IFX_REG_W32(
[all...]
H A Difxmips_ptm_ar9.c144 IFX_REG_W32(1, SB_MST_PRI0);
145 IFX_REG_W32(1, SB_MST_PRI1);
148 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
149 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
150 IFX_REG_W32(0x000000FF, EMA_IER);
151 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
156 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
157 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
158 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
159 IFX_REG_W32(
[all...]
H A Difxmips_ptm_adsl.h40 #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) macro
42 #define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
H A Difxmips_ptm_vdsl.h36 #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) macro
38 #define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
H A Difxmips_ptm_vdsl.c547 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
794 IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));
795 IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));
796 IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));
797 IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));
798 IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));
799 IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));
800 IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));
801 IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));
802 IFX_REG_W32(
[all...]
H A Difxmips_ptm_adsl.c676 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
711 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf + 16), MBOX_IGU3_ISRS);
716 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf), MBOX_IGU3_ISRS);
1335 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1338 IFX_REG_W32(0, p);
1343 IFX_REG_W32(write_desc_delay, CFG_WAN_WRDES_DELAY);
1344 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER) - 1, CFG_WRX_DMACH_ON);
1345 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1, CFG_WTX_DMACH_ON);
1347 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH); // WAN RX EFM-TC Looking Threshold
1349 IFX_REG_W32(eth_efmtc_crc_cf
[all...]
/openwrt/package/kernel/lantiq/ltq-atm/src/
H A Difxmips_atm_amazon_se.c174 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
175 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
176 IFX_REG_W32(0x000000FF, EMA_IER);
177 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
182 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
183 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
184 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
185 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
190 IFX_REG_W32(0x0000, DREG_AT_CTRL);
191 IFX_REG_W32(
[all...]
H A Difxmips_atm_danube.c117 IFX_REG_W32(0x00, CDM_CFG);
119 IFX_REG_W32(0x04, CDM_CFG);
124 IFX_REG_W32(*code_src++, dest++);
129 IFX_REG_W32(*data_src++, dest++);
158 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
159 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
160 IFX_REG_W32(0x000000FF, EMA_IER);
161 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
164 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
165 IFX_REG_W32(
[all...]
H A Difxmips_atm_ar9.c138 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
139 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
140 IFX_REG_W32(0x000000FF, EMA_IER);
141 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
146 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
147 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
148 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
149 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
158 IFX_REG_W32(0, p++);
170 IFX_REG_W32(
[all...]
H A Difxmips_atm_vr9.c94 IFX_REG_W32(*code_src++, dest++);
98 IFX_REG_W32(*data_src++, dest++);
126 IFX_REG_W32(0x08, PDMA_CFG);
127 IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
128 IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
131 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
132 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
133 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
134 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
143 IFX_REG_W32(
[all...]
H A Difxmips_atm_core.h31 #define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) macro
33 #define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
H A Dltq_atm.c1745 IFX_REG_W32(0x0F, UTP_CFG);
1764 IFX_REG_W32(0x00, UTP_CFG);

Completed in 62 milliseconds