Lines Matching refs:IFX_REG_W32
676 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
711 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf + 16), MBOX_IGU3_ISRS);
716 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf), MBOX_IGU3_ISRS);
1335 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1338 IFX_REG_W32(0, p);
1343 IFX_REG_W32(write_desc_delay, CFG_WAN_WRDES_DELAY);
1344 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER) - 1, CFG_WRX_DMACH_ON);
1345 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1, CFG_WTX_DMACH_ON);
1347 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH); // WAN RX EFM-TC Looking Threshold
1349 IFX_REG_W32(eth_efmtc_crc_cfg, CFG_ETH_EFMTC_CRC);
1493 IFX_REG_W32(0, MBOX_IGU1_IER);
1494 IFX_REG_W32(~0, MBOX_IGU1_ISRC);