ltq-ptm/src/ifxmips_ptm_vr9.c

102     IFX_REG_W32(0x00000001, PDMA_CFG);
103     IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);
104     IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);
105     IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);
106     IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);
108     IFX_REG_W32(0x00000011, SAR_MODE_CFG);
109     IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);
110     IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);
111     IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);
112     IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1);
113     IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2);
114     IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG);
116     IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG);
117     IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG);
122     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
123     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
124     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
125     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
130     IFX_REG_W32(0x00010040, SFSM_CFG0);
131     IFX_REG_W32(0x00010040, SFSM_CFG1);
132     IFX_REG_W32(0x00020000, SFSM_PGCNT0);
133     IFX_REG_W32(0x00020000, SFSM_PGCNT1);
134     IFX_REG_W32(0x00000000, DREG_AT_IDLE0);
135     IFX_REG_W32(0x00000000, DREG_AT_IDLE1);
136     IFX_REG_W32(0x00000000, DREG_AR_IDLE0);
137     IFX_REG_W32(0x00000000, DREG_AR_IDLE1);
138     IFX_REG_W32(0x0000080C, DREG_B0_LADR);
139     IFX_REG_W32(0x0000080C, DREG_B1_LADR);
141     IFX_REG_W32(0x000001F0, DREG_AR_CFG0);
142     IFX_REG_W32(0x000001F0, DREG_AR_CFG1);
143     IFX_REG_W32(0x000001E0, DREG_AT_CFG0);
144     IFX_REG_W32(0x000001E0, DREG_AT_CFG1);
147     //IFX_REG_W32(0, SFSM_STATE0);
148     //IFX_REG_W32(0, SFSM_STATE1);
156     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
157     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
158     IFX_REG_W32(0x00030028, FFSM_CFG0);         //  Force_idle
159     IFX_REG_W32(0x00030028, FFSM_CFG1);
169         IFX_REG_W32(0, p++);
173         IFX_REG_W32(0, p++);
206         IFX_REG_W32(*code_src++, dest++);
211         IFX_REG_W32(*data_src++, dest++);