ltq-ptm/src/ifxmips_ptm_ar9.c

144     IFX_REG_W32(1, SB_MST_PRI0);
145     IFX_REG_W32(1, SB_MST_PRI1);
148     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
149     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
150     IFX_REG_W32(0x000000FF, EMA_IER);
151     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
156     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
157     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
158     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
159     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
164     IFX_REG_W32(0x0,        RFBI_CFG);
165     IFX_REG_W32(0x1800,     SFSM_DBA0);
166     IFX_REG_W32(0x1921,     SFSM_DBA1);
167     IFX_REG_W32(0x1A42,     SFSM_CBA0);
168     IFX_REG_W32(0x1A53,     SFSM_CBA1);
169     IFX_REG_W32(0x14011,    SFSM_CFG0);
170     IFX_REG_W32(0x14011,    SFSM_CFG1);
171     IFX_REG_W32(0x1000,     FFSM_DBA0);
172     IFX_REG_W32(0x1700,     FFSM_DBA1);
173     IFX_REG_W32(0x3000C,    FFSM_CFG0);
174     IFX_REG_W32(0x3000C,    FFSM_CFG1);
175     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
176     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
194         IFX_REG_W32(0x40020000, SW_P2_CTL);
198         IFX_REG_W32(0x00007028, DM_RXCFG);
199         IFX_REG_W32(0x00007028, DS_RXCFG);
201         IFX_REG_W32(0x00001100, DM_RXDB);
202         IFX_REG_W32(0x00001100, DS_RXDB);
204         IFX_REG_W32(0x00001600, DM_RXCB);
205         IFX_REG_W32(0x00001600, DS_RXCB);
211         IFX_REG_W32(0x0, DM_RXPGCNT);
212         IFX_REG_W32(0x0, DS_RXPGCNT);
213         IFX_REG_W32(0x0, DM_RXPKTCNT);
219         IFX_REG_W32(temp, SW_P2_CTL);
230         IFX_REG_W32(0, p++);
252         IFX_REG_W32(0x00, CDM_CFG);
254         IFX_REG_W32(0x04, CDM_CFG);
259         IFX_REG_W32(*code_src++, dest++);
264         IFX_REG_W32(*data_src++, dest++);
325     IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
344     IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));