Lines Matching refs:IFX_REG_W32
164 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
165 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
166 IFX_REG_W32(0x000000FF, EMA_IER);
167 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
172 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
173 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
174 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
175 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
180 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
181 IFX_REG_W32(0x3C00, DREG_AR_CTRL);
182 IFX_REG_W32(0x0, DREG_AT_IDLE0);
183 IFX_REG_W32(0x0, DREG_AT_IDLE1);
184 IFX_REG_W32(0x0, DREG_AR_IDLE0);
185 IFX_REG_W32(0x0, DREG_AR_IDLE1);
186 IFX_REG_W32(0x0, RFBI_CFG);
187 IFX_REG_W32(0x0200, SFSM_DBA0);
188 IFX_REG_W32(0x0800, SFSM_DBA1);
189 IFX_REG_W32(0x0321, SFSM_CBA0);
190 IFX_REG_W32(0x0921, SFSM_CBA1);
191 IFX_REG_W32(0x14011, SFSM_CFG0);
192 IFX_REG_W32(0x14011, SFSM_CFG1);
193 IFX_REG_W32(0x0332, FFSM_DBA0);
194 IFX_REG_W32(0x0932, FFSM_DBA1);
195 IFX_REG_W32(0x3000C, FFSM_CFG0);
196 IFX_REG_W32(0x3000C, FFSM_CFG1);
197 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
198 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
207 IFX_REG_W32(0, p++);
229 IFX_REG_W32(0x00, CDM_CFG);
231 IFX_REG_W32(0x04, CDM_CFG);
236 IFX_REG_W32(*code_src++, dest++);
241 IFX_REG_W32(*data_src++, dest++);
302 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(pp32));
321 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(pp32));