Lines Matching refs:IFX_REG_W32
159 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
160 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
161 IFX_REG_W32(0x000000FF, EMA_IER);
162 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
167 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
168 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
169 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
170 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
175 IFX_REG_W32(0x0F00, DREG_AT_CTRL);
176 IFX_REG_W32(0x3C00, DREG_AR_CTRL);
177 IFX_REG_W32(0x0, DREG_AT_IDLE0);
178 IFX_REG_W32(0x0, DREG_AT_IDLE1);
179 IFX_REG_W32(0x0, DREG_AR_IDLE0);
180 IFX_REG_W32(0x0, DREG_AR_IDLE1);
181 IFX_REG_W32(0x0, RFBI_CFG);
182 IFX_REG_W32(0x1600, SFSM_DBA0);
183 IFX_REG_W32(0x1721, SFSM_DBA1);
184 IFX_REG_W32(0x1842, SFSM_CBA0);
185 IFX_REG_W32(0x1853, SFSM_CBA1);
186 IFX_REG_W32(0x14011, SFSM_CFG0);
187 IFX_REG_W32(0x14011, SFSM_CFG1);
188 IFX_REG_W32(0x1864, FFSM_DBA0);
189 IFX_REG_W32(0x1930, FFSM_DBA1);
190 IFX_REG_W32(0x3000C, FFSM_CFG0);
191 IFX_REG_W32(0x3000C, FFSM_CFG1);
192 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
193 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
202 IFX_REG_W32(0, p++);
224 IFX_REG_W32(0x00, CDM_CFG);
226 IFX_REG_W32(0x04, CDM_CFG);
231 IFX_REG_W32(*code_src++, dest++);
236 IFX_REG_W32(*data_src++, dest++);
297 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
316 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);