Lines Matching refs:IFX_REG_W32
117 IFX_REG_W32(0x00, CDM_CFG);
119 IFX_REG_W32(0x04, CDM_CFG);
124 IFX_REG_W32(*code_src++, dest++);
129 IFX_REG_W32(*data_src++, dest++);
158 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
159 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
160 IFX_REG_W32(0x000000FF, EMA_IER);
161 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
164 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
165 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
166 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
167 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
170 IFX_REG_W32(0x0000, DREG_AT_CTRL);
171 IFX_REG_W32(0x0000, DREG_AR_CTRL);
172 IFX_REG_W32(0x0, DREG_AT_IDLE0);
173 IFX_REG_W32(0x0, DREG_AT_IDLE1);
174 IFX_REG_W32(0x0, DREG_AR_IDLE0);
175 IFX_REG_W32(0x0, DREG_AR_IDLE1);
176 IFX_REG_W32(0x40, RFBI_CFG);
177 IFX_REG_W32(0x1600, SFSM_DBA0);
178 IFX_REG_W32(0x1718, SFSM_DBA1);
179 IFX_REG_W32(0x1830, SFSM_CBA0);
180 IFX_REG_W32(0x1844, SFSM_CBA1);
181 IFX_REG_W32(0x14014, SFSM_CFG0);
182 IFX_REG_W32(0x14014, SFSM_CFG1);
183 IFX_REG_W32(0x1858, FFSM_DBA0);
184 IFX_REG_W32(0x18AC, FFSM_DBA1);
185 IFX_REG_W32(0x10006, FFSM_CFG0);
186 IFX_REG_W32(0x10006, FFSM_CFG1);
187 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
188 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
191 IFX_REG_W32(0, p++);
210 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
220 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);