Lines Matching refs:IFX_REG_W32
138 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
139 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
140 IFX_REG_W32(0x000000FF, EMA_IER);
141 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
146 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
147 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
148 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
149 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
158 IFX_REG_W32(0, p++);
170 IFX_REG_W32(0x00, CDM_CFG);
172 IFX_REG_W32(0x04, CDM_CFG);
177 IFX_REG_W32(*code_src++, dest++);
182 IFX_REG_W32(*data_src++, dest++);
224 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
233 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));