Searched refs:ARM (Results 1 - 25 of 70) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features ------*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
17 #include "ARM.h"
26 case ARM::tADC:
27 case ARM::tADDi3:
28 case ARM::tADDi8:
29 case ARM::tADDrSPi:
30 case ARM::tADDrr:
31 case ARM
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H A DARMExpandPseudoInsts.cpp18 #include "ARM.h"
34 cl::desc("Verify machine code after expanding ARM pseudos"));
50 return "ARM pseudo instruction expansion pass";
131 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
132 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
133 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
134 { ARM
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H A DARMInstrInfo.cpp1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
15 #include "ARM.h"
39 NopInst.setOpcode(ARM::HINT);
44 NopInst.setOpcode(ARM::MOVr);
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM
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H A DThumb2InstrInfo.cpp15 #include "ARM.h"
39 NopInst.setOpcode(ARM::tHINT);
81 if (MBBI->getOpcode() == ARM::t2IT) {
119 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
122 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
142 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
143 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
144 RC == &ARM
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H A DThumb2SizeReduction.cpp11 #include "ARM.h"
62 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
63 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
64 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
65 { ARM
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H A DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
70 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
71 { ARM::VMLSS, ARM
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H A DARMFPUName.h1 //===-- ARMFPUName.h - List of the ARM FPU names ----------------*- C++ -*-===//
14 namespace ARM { namespace in namespace:llvm
23 } // namespace ARM
H A DARMAsmPrinter.cpp1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
17 #include "ARM.h"
70 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
76 unsigned SReg = Reg - ARM::S0;
97 } else if (Reg >= ARM
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H A DARMLoadStoreOptimizer.cpp1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
16 #include "ARM.h"
75 return "ARM load / store optimization pass";
144 case ARM::LDRi12:
148 case ARM_AM::ia: return ARM::LDMIA;
149 case ARM_AM::da: return ARM::LDMDA;
150 case ARM_AM::db: return ARM::LDMDB;
151 case ARM_AM::ib: return ARM::LDMIB;
153 case ARM::STRi12:
157 case ARM_AM::ia: return ARM
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H A DARMFrameLowering.cpp1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
67 // stack frame. ARM (especially Thumb) has small immediate offset to
97 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
98 MI->getOpcode() == ARM::LDR_POST_REG ||
99 MI->getOpcode() == ARM::t2LDR_POST) &&
101 MI->getOperand(1).getReg() == ARM::SP)
128 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM
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H A DARMISelDAGToDAG.cpp1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
10 // This file defines an instruction selector for the ARM target.
15 #include "ARM.h"
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
77 return "ARM Instruction Selection";
136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
208 /// ARM.
246 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
409 /// least on current ARM implementation
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H A DARMRelocations.h1 //===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
10 // This file defines the ARM target-specific relocation types.
20 namespace ARM { namespace in namespace:llvm
38 // reloc_arm_machine_cp_entry - Relocation of a ARM machine constantpool
H A DThumb1InstrInfo.cpp15 #include "ARM.h"
30 NopInst.setOpcode(ARM::tMOVr);
31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
56 assert((RC == &ARM::tGPRRegClass ||
60 if (RC == &ARM::tGPRRegClass ||
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
84 assert((RC == &ARM
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H A DThumb1FrameLowering.cpp27 // stack frame. ARM (especially Thumb) has small immediate offset to
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
123 case ARM::R4:
124 case ARM::R5:
125 case ARM
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H A DARMBaseRegisterInfo.cpp1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
15 #include "ARM.h"
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
49 BasePtr(ARM::R6) {
121 Reserved.set(ARM::SP);
122 Reserved.set(ARM
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H A DARMCallingConv.h1 //=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
10 // This file contains the custom routines for the ARM Calling Convention that
18 #include "ARM.h"
31 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
75 static const uint16_t LoRegList[] = { ARM
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
54 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
57 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
61 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
154 case ARM::tBcc: return ARM::t2Bcc;
155 case ARM::tLDRpci: return ARM::t2LDRpci;
156 case ARM::tADR: return ARM
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H A DARMELFObjectWriter.cpp1 //===-- ARMELFObjectWriter.cpp - ARM ELF Writer ---------------------------===//
55 // In ARM, _MergedGlobals and other most symbols get emitted directly.
57 // This code is an approximation of what ARM/gcc does.
176 case ARM::fixup_arm_blx:
177 case ARM::fixup_arm_uncondbl:
187 case ARM::fixup_arm_condbl:
188 case ARM::fixup_arm_condbranch:
189 case ARM::fixup_arm_uncondbranch:
192 case ARM::fixup_t2_condbranch:
193 case ARM
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H A DARMMachObjectWriter.cpp1 //===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
86 case ARM::fixup_arm_ldst_pcrel_12:
87 case ARM::fixup_arm_pcrel_10:
88 case ARM::fixup_arm_adr_pcrel_12:
89 case ARM::fixup_arm_condbranch:
90 case ARM::fixup_arm_uncondbranch:
91 case ARM::fixup_arm_uncondbl:
92 case ARM::fixup_arm_condbl:
93 case ARM::fixup_arm_blx:
100 case ARM
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/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
447 // VFP and NEON instructions, similarly, are shared between ARM
570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
591 case ARM
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/freebsd-10.2-release/lib/clang/libllvmarmasmparser/
H A DMakefile7 SRCDIR= lib/Target/ARM/AsmParser
8 INCDIR= lib/Target/ARM
/freebsd-10.2-release/lib/clang/libllvmarmdisassembler/
H A DMakefile7 SRCDIR= lib/Target/ARM/Disassembler
8 INCDIR= lib/Target/ARM
/freebsd-10.2-release/lib/clang/libllvmarminfo/
H A DMakefile7 SRCDIR= lib/Target/ARM/TargetInfo
8 INCDIR= lib/Target/ARM
/freebsd-10.2-release/lib/clang/libllvmarminstprinter/
H A DMakefile7 SRCDIR= lib/Target/ARM/InstPrinter
8 INCDIR= lib/Target/ARM
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
162 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
165 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
168 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
171 return STI.getFeatureBits() & ARM::HasV4TOps;
174 return STI.getFeatureBits() & ARM::HasV6Ops;
177 return STI.getFeatureBits() & ARM::HasV6MOps;
180 return STI.getFeatureBits() & ARM::HasV7Ops;
183 return STI.getFeatureBits() & ARM::HasV8Ops;
186 return !(STI.getFeatureBits() & ARM
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