Lines Matching refs:ARM
1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
67 // stack frame. ARM (especially Thumb) has small immediate offset to
97 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
98 MI->getOpcode() == ARM::LDR_POST_REG ||
99 MI->getOpcode() == ARM::t2LDR_POST) &&
101 MI->getOperand(1).getReg() == ARM::SP)
128 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
178 case ARM::R0:
179 case ARM::R1:
180 case ARM::R2:
181 case ARM::R3:
182 case ARM::R4:
183 case ARM::R5:
184 case ARM::R6:
185 case ARM::R7:
186 case ARM::LR:
191 case ARM::R8:
192 case ARM::R9:
193 case ARM::R10:
194 case ARM::R11:
195 case ARM::R12:
205 if (Reg == ARM::D8)
207 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
242 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
267 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
286 FramePtr, ARM::SP, FramePtrOffsetInPush,
308 TII.get(ARM::BICri), ARM::SP)
309 .addReg(ARM::SP, RegState::Kill)
318 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
319 .addReg(ARM::SP, RegState::Kill));
321 TII.get(ARM::t2BICri), ARM::R4)
322 .addReg(ARM::R4, RegState::Kill)
324 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
325 .addReg(ARM::R4, RegState::Kill));
339 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
340 .addReg(ARM::SP)
343 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
345 .addReg(ARM::SP));
405 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
415 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
417 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
419 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
420 ARM::SP)
421 .addReg(ARM::R4));
424 // Thumb2 or ARM.
426 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
429 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
430 ARM::SP)
441 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
448 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
454 if (RetOpcode == ARM::TCRETURNdi) {
456 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
457 ARM::TAILJMPd;
470 } else if (RetOpcode == ARM::TCRETURNri) {
472 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
511 FrameReg = ARM::SP;
604 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
612 if (Reg == ARM::LR) {
634 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
635 .addReg(ARM::SP).setMIFlags(MIFlags));
640 ARM::SP)
642 .addReg(ARM::SP).setMIFlags(MIFlags)
662 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
663 RetOpcode == ARM::TCRETURNri);
665 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
677 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
680 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
682 Reg = ARM::PC;
683 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
702 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
703 .addReg(ARM::SP));
714 if (Regs[0] == ARM::PC)
715 Regs[0] = ARM::LR;
718 .addReg(ARM::SP, RegState::Define)
719 .addReg(ARM::SP);
720 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
722 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
751 unsigned DNum = CSI[i].getReg() - ARM::D8;
782 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
783 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
784 .addReg(ARM::SP)
788 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
790 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
791 .addReg(ARM::R4, RegState::Kill)
798 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
799 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
800 .addReg(ARM::R4);
807 unsigned NextReg = ARM::D8;
812 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
813 &ARM::QQPRRegClass);
815 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
816 ARM::R4)
817 .addReg(ARM::R4, RegState::Kill).addImm(16)
830 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
831 &ARM::QQPRRegClass);
833 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
834 .addReg(ARM::R4).addImm(16).addReg(NextReg)
842 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
843 &ARM::QPRRegClass);
845 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
846 .addReg(ARM::R4).addImm(16).addReg(SupReg));
855 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
857 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
861 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
886 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
908 if (CSI[i].getReg() == ARM::D8) {
921 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
922 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
926 unsigned NextReg = ARM::D8;
930 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
931 &ARM::QQPRRegClass);
932 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
933 .addReg(ARM::R4, RegState::Define)
934 .addReg(ARM::R4, RegState::Kill).addImm(16)
946 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
947 &ARM::QQPRRegClass);
948 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
949 .addReg(ARM::R4).addImm(16)
957 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
958 &ARM::QPRRegClass);
959 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
960 .addReg(ARM::R4).addImm(16));
967 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
968 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
971 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
984 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
986 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
987 unsigned FltOpc = ARM::VSTMDDB_UPD;
1022 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1023 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1024 unsigned FltOpc = ARM::VLDMDIA_UPD;
1065 if (I->getOpcode() == ARM::ADDri) {
1138 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1149 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1181 MRI.setPhysRegUsed(ARM::R4);
1186 MRI.setPhysRegUsed(ARM::LR);
1196 MRI.setPhysRegUsed(ARM::R4);
1217 if (!ARM::GPRRegClass.contains(Reg))
1224 if (Reg == ARM::LR)
1232 case ARM::LR:
1235 case ARM::R0: case ARM::R1:
1236 case ARM::R2: case ARM::R3:
1237 case ARM::R4: case ARM::R5:
1238 case ARM::R6: case ARM::R7:
1251 case ARM::R0: case ARM::R1:
1252 case ARM::R2: case ARM::R3:
1253 case ARM::R4: case ARM::R5:
1254 case ARM::R6: case ARM::R7:
1255 case ARM::LR:
1306 MRI.setPhysRegUsed(ARM::LR);
1310 (unsigned)ARM::LR);
1333 isARMLowRegister(Reg) || Reg == ARM::LR) {
1363 Reg == ARM::LR)) {
1386 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1395 MRI.setPhysRegUsed(ARM::LR);
1430 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1438 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);