Lines Matching refs:ARM
1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
17 #include "ARM.h"
70 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
76 unsigned SReg = Reg - ARM::S0;
97 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
103 unsigned QReg = Reg - ARM::Q0;
178 if(ARM::GPRPairRegClass.contains(Reg)) {
181 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
284 if (!ARM::DPRRegClass.contains(*SR))
286 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
311 if (ARM::GPRPairRegClass.contains(RegBegin)) {
313 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
315 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
362 if (RC == ARM::GPRPairRegClassID) {
370 ARM::gsub_0 : ARM::gsub_1);
392 if (!ARM::QPRRegClass.contains(Reg))
396 ARM::dsub_0 : ARM::dsub_1);
411 if(!ARM::GPRPairRegClass.contains(Reg))
413 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
457 // the way symbol offsets are encoded with the current Darwin ARM
505 // Emit ARM Build Attributes
583 // to appear in the .ARM.attributes section in ELF.
653 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
655 ATS.emitFPU(ARM::NEON_FP_ARMV8);
658 ATS.emitFPU(ARM::NEON_VFPV4);
660 ATS.emitFPU(ARM::NEON);
667 ATS.emitFPU(ARM::FP_ARMV8);
669 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
671 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
673 ATS.emitFPU(ARM::VFPV2);
713 // Check if hardware divide is only available in thumb2 or ARM as well.
856 if (Opcode == ARM::BR_JTadd)
858 else if (Opcode == ARM::BR_JTm)
906 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
919 if (MI->getOpcode() == ARM::t2TBB_JT) {
923 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
935 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
979 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
985 SrcReg = DstReg = ARM::SP;
994 assert(DstReg == ARM::SP &&
1007 case ARM::tPUSH:
1010 case ARM::STMDB_UPD:
1011 case ARM::t2STMDB_UPD:
1012 case ARM::VSTMDDB_UPD:
1013 assert(SrcReg == ARM::SP &&
1025 case ARM::STR_PRE_IMM:
1026 case ARM::STR_PRE_REG:
1027 case ARM::t2STR_PRE:
1028 assert(MI->getOperand(2).getReg() == ARM::SP &&
1033 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1036 if (SrcReg == ARM::SP) {
1042 case ARM::MOVr:
1043 case ARM::tMOVr:
1046 case ARM::ADDri:
1049 case ARM::SUBri:
1050 case ARM::t2SUBri:
1053 case ARM::tSUBspi:
1056 case ARM::tADDspi:
1057 case ARM::tADDrSPi:
1060 case ARM::tLDRpci: {
1078 if (DstReg == FramePtr && FramePtr != ARM::SP)
1081 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1082 else if (DstReg == ARM::SP) {
1090 } else if (DstReg == ARM::SP) {
1110 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1129 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1130 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1131 case ARM::LEApcrel:
1132 case ARM::tLEApcrel:
1133 case ARM::t2LEApcrel: {
1137 ARM::t2LEApcrel ? ARM::t2ADR
1138 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1139 : ARM::ADR))
1147 case ARM::LEApcrelJT:
1148 case ARM::tLEApcrelJT:
1149 case ARM::t2LEApcrelJT: {
1154 ARM::t2LEApcrelJT ? ARM::t2ADR
1155 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1156 : ARM::ADR))
1166 case ARM::BX_CALL: {
1167 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1168 .addReg(ARM::LR)
1169 .addReg(ARM::PC)
1176 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1180 case ARM::tBX_CALL: {
1181 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1182 .addReg(ARM::LR)
1183 .addReg(ARM::PC)
1188 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1195 case ARM::BMOVPCRX_CALL: {
1196 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1197 .addReg(ARM::LR)
1198 .addReg(ARM::PC)
1205 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1206 .addReg(ARM::PC)
1215 case ARM::BMOVPCB_CALL: {
1216 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1217 .addReg(ARM::LR)
1218 .addReg(ARM::PC)
1228 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1235 case ARM::MOVi16_ga_pcrel:
1236 case ARM::t2MOVi16_ga_pcrel: {
1238 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1251 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1271 case ARM::MOVTi16_ga_pcrel:
1272 case ARM::t2MOVTi16_ga_pcrel: {
1274 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1275 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1289 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1308 case ARM::tPICADD: {
1320 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1323 .addReg(ARM::PC)
1329 case ARM::PICADD: {
1341 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1343 .addReg(ARM::PC)
1352 case ARM::PICSTR:
1353 case ARM::PICSTRB:
1354 case ARM::PICSTRH:
1355 case ARM::PICLDR:
1356 case ARM::PICLDRB:
1357 case ARM::PICLDRH:
1358 case ARM::PICLDRSB:
1359 case ARM::PICLDRSH: {
1376 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1377 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1378 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1379 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1380 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1381 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1382 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1383 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1387 .addReg(ARM::PC)
1396 case ARM::CONSTPOOL_ENTRY: {
1420 case ARM::t2BR_JT: {
1422 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1423 .addReg(ARM::PC)
1433 case ARM::t2TBB_JT: {
1435 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1436 .addReg(ARM::PC)
1448 case ARM::t2TBH_JT: {
1450 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1451 .addReg(ARM::PC)
1461 case ARM::tBR_JTr:
1462 case ARM::BR_JTr: {
1466 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1467 ARM::MOVr : ARM::tMOVr;
1469 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1475 if (Opc == ARM::MOVr)
1480 if (Opc == ARM::tMOVr)
1487 case ARM::BR_JTm: {
1493 TmpInst.setOpcode(ARM::LDRi12);
1494 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1498 TmpInst.setOpcode(ARM::LDRrs);
1499 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1513 case ARM::BR_JTadd: {
1516 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1517 .addReg(ARM::PC)
1530 case ARM::TRAP: {
1542 case ARM::TRAPNaCl: {
1549 case ARM::tTRAP: {
1561 case ARM::t2Int_eh_sjlj_setjmp:
1562 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1563 case ARM::tInt_eh_sjlj_setjmp: {
1576 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1578 .addReg(ARM::PC)
1583 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1586 .addReg(ARM::CPSR)
1593 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1603 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1604 .addReg(ARM::R0)
1605 .addReg(ARM::CPSR)
1612 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1618 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1619 .addReg(ARM::R0)
1620 .addReg(ARM::CPSR)
1630 case ARM::Int_eh_sjlj_setjmp_nofp:
1631 case ARM::Int_eh_sjlj_setjmp: {
1642 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1644 .addReg(ARM::PC)
1652 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1660 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1661 .addReg(ARM::R0)
1669 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1670 .addReg(ARM::PC)
1671 .addReg(ARM::PC)
1680 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1681 .addReg(ARM::R0)
1690 case ARM::Int_eh_sjlj_longjmp: {
1697 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1698 .addReg(ARM::SP)
1705 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1713 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1714 .addReg(ARM::R7)
1721 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1728 case ARM::tInt_eh_sjlj_longjmp: {
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1746 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1747 .addReg(ARM::SP)
1753 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1761 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1762 .addReg(ARM::R7)
1769 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)