Lines Matching refs:ARM
1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
447 // VFP and NEON instructions, similarly, are shared between ARM
570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
591 case ARM::tBcc:
592 case ARM::t2Bcc:
593 case ARM::tCBZ:
594 case ARM::tCBNZ:
595 case ARM::tCPS:
596 case ARM::t2CPS3p:
597 case ARM::t2CPS2p:
598 case ARM::t2CPS1p:
599 case ARM::tMOVSr:
600 case ARM::tSETEND:
608 case ARM::tB:
609 case ARM::t2B:
610 case ARM::t2TBB:
611 case ARM::t2TBH:
641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
657 // encodings between ARM and Thumb modes, and they are predicable in ARM
677 I->setReg(ARM::CPSR);
692 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
693 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
737 if (MI.getOpcode() == ARM::t2IT) {
870 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
871 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
872 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
873 ARM::R12, ARM::SP, ARM::LR, ARM::PC
906 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
922 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
923 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
946 Register = ARM::R0;
949 Register = ARM::R1;
952 Register = ARM::R2;
955 Register = ARM::R3;
958 Register = ARM::R9;
961 Register = ARM::R12;
981 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
982 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
983 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
984 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1062 ARM::Q15
1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 case ARM::t2STMIA_UPD:
1218 case ARM::t2STMDB_UPD:
1327 case ARM::LDC_OFFSET:
1328 case ARM::LDC_PRE:
1329 case ARM::LDC_POST:
1330 case ARM::LDC_OPTION:
1331 case ARM::LDCL_OFFSET:
1332 case ARM::LDCL_PRE:
1333 case ARM::LDCL_POST:
1334 case ARM::LDCL_OPTION:
1335 case ARM::STC_OFFSET:
1336 case ARM::STC_PRE:
1337 case ARM::STC_POST:
1338 case ARM::STC_OPTION:
1339 case ARM::STCL_OFFSET:
1340 case ARM::STCL_PRE:
1341 case ARM::STCL_POST:
1342 case ARM::STCL_OPTION:
1343 case ARM::t2LDC_OFFSET:
1344 case ARM::t2LDC_PRE:
1345 case ARM::t2LDC_POST:
1346 case ARM::t2LDC_OPTION:
1347 case ARM::t2LDCL_OFFSET:
1348 case ARM::t2LDCL_PRE:
1349 case ARM::t2LDCL_POST:
1350 case ARM::t2LDCL_OPTION:
1351 case ARM::t2STC_OFFSET:
1352 case ARM::t2STC_PRE:
1353 case ARM::t2STC_POST:
1354 case ARM::t2STC_OPTION:
1355 case ARM::t2STCL_OFFSET:
1356 case ARM::t2STCL_PRE:
1357 case ARM::t2STCL_POST:
1358 case ARM::t2STCL_OPTION:
1368 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1377 case ARM::t2LDC2_OFFSET:
1378 case ARM::t2LDC2L_OFFSET:
1379 case ARM::t2LDC2_PRE:
1380 case ARM::t2LDC2L_PRE:
1381 case ARM::t2STC2_OFFSET:
1382 case ARM::t2STC2L_OFFSET:
1383 case ARM::t2STC2_PRE:
1384 case ARM::t2STC2L_PRE:
1385 case ARM::LDC2_OFFSET:
1386 case ARM::LDC2L_OFFSET:
1387 case ARM::LDC2_PRE:
1388 case ARM::LDC2L_PRE:
1389 case ARM::STC2_OFFSET:
1390 case ARM::STC2L_OFFSET:
1391 case ARM::STC2_PRE:
1392 case ARM::STC2L_PRE:
1393 case ARM::t2LDC_OFFSET:
1394 case ARM::t2LDCL_OFFSET:
1395 case ARM::t2LDC_PRE:
1396 case ARM::t2LDCL_PRE:
1397 case ARM::t2STC_OFFSET:
1398 case ARM::t2STCL_OFFSET:
1399 case ARM::t2STC_PRE:
1400 case ARM::t2STCL_PRE:
1401 case ARM::LDC_OFFSET:
1402 case ARM::LDCL_OFFSET:
1403 case ARM::LDC_PRE:
1404 case ARM::LDCL_PRE:
1405 case ARM::STC_OFFSET:
1406 case ARM::STCL_OFFSET:
1407 case ARM::STC_PRE:
1408 case ARM::STCL_PRE:
1412 case ARM::t2LDC2_POST:
1413 case ARM::t2LDC2L_POST:
1414 case ARM::t2STC2_POST:
1415 case ARM::t2STC2L_POST:
1416 case ARM::LDC2_POST:
1417 case ARM::LDC2L_POST:
1418 case ARM::STC2_POST:
1419 case ARM::STC2L_POST:
1420 case ARM::t2LDC_POST:
1421 case ARM::t2LDCL_POST:
1422 case ARM::t2STC_POST:
1423 case ARM::t2STCL_POST:
1424 case ARM::LDC_POST:
1425 case ARM::LDCL_POST:
1426 case ARM::STC_POST:
1427 case ARM::STCL_POST:
1438 case ARM::LDC_OFFSET:
1439 case ARM::LDC_PRE:
1440 case ARM::LDC_POST:
1441 case ARM::LDC_OPTION:
1442 case ARM::LDCL_OFFSET:
1443 case ARM::LDCL_PRE:
1444 case ARM::LDCL_POST:
1445 case ARM::LDCL_OPTION:
1446 case ARM::STC_OFFSET:
1447 case ARM::STC_PRE:
1448 case ARM::STC_POST:
1449 case ARM::STC_OPTION:
1450 case ARM::STCL_OFFSET:
1451 case ARM::STCL_PRE:
1452 case ARM::STCL_POST:
1453 case ARM::STCL_OPTION:
1480 case ARM::STR_POST_IMM:
1481 case ARM::STR_POST_REG:
1482 case ARM::STRB_POST_IMM:
1483 case ARM::STRB_POST_REG:
1484 case ARM::STRT_POST_REG:
1485 case ARM::STRT_POST_IMM:
1486 case ARM::STRBT_POST_REG:
1487 case ARM::STRBT_POST_IMM:
1500 case ARM::LDR_POST_IMM:
1501 case ARM::LDR_POST_REG:
1502 case ARM::LDRB_POST_IMM:
1503 case ARM::LDRB_POST_REG:
1504 case ARM::LDRBT_POST_REG:
1505 case ARM::LDRBT_POST_IMM:
1506 case ARM::LDRT_POST_REG:
1507 case ARM::LDRT_POST_IMM:
1633 case ARM::STRD:
1634 case ARM::STRD_PRE:
1635 case ARM::STRD_POST:
1636 case ARM::LDRD:
1637 case ARM::LDRD_PRE:
1638 case ARM::LDRD_POST:
1645 case ARM::STRD:
1646 case ARM::STRD_PRE:
1647 case ARM::STRD_POST:
1660 case ARM::STRH:
1661 case ARM::STRH_PRE:
1662 case ARM::STRH_POST:
1670 case ARM::LDRD:
1671 case ARM::LDRD_PRE:
1672 case ARM::LDRD_POST:
1687 case ARM::LDRH:
1688 case ARM::LDRH_PRE:
1689 case ARM::LDRH_POST:
1702 case ARM::LDRSH:
1703 case ARM::LDRSH_PRE:
1704 case ARM::LDRSH_POST:
1705 case ARM::LDRSB:
1706 case ARM::LDRSB_PRE:
1707 case ARM::LDRSB_POST:
1732 case ARM::STRD:
1733 case ARM::STRD_PRE:
1734 case ARM::STRD_POST:
1735 case ARM::STRH:
1736 case ARM::STRH_PRE:
1737 case ARM::STRH_POST:
1749 case ARM::STRD:
1750 case ARM::STRD_PRE:
1751 case ARM::STRD_POST:
1752 case ARM::LDRD:
1753 case ARM::LDRD_PRE:
1754 case ARM::LDRD_POST:
1765 case ARM::LDRD:
1766 case ARM::LDRD_PRE:
1767 case ARM::LDRD_POST:
1768 case ARM::LDRH:
1769 case ARM::LDRH_PRE:
1770 case ARM::LDRH_POST:
1771 case ARM::LDRSH:
1772 case ARM::LDRSH_PRE:
1773 case ARM::LDRSH_POST:
1774 case ARM::LDRSB:
1775 case ARM::LDRSB_PRE:
1776 case ARM::LDRSB_POST:
1777 case ARM::LDRHTr:
1778 case ARM::LDRSBTr:
1869 case ARM::LDMDA:
1870 Inst.setOpcode(ARM::RFEDA);
1872 case ARM::LDMDA_UPD:
1873 Inst.setOpcode(ARM::RFEDA_UPD);
1875 case ARM::LDMDB:
1876 Inst.setOpcode(ARM::RFEDB);
1878 case ARM::LDMDB_UPD:
1879 Inst.setOpcode(ARM::RFEDB_UPD);
1881 case ARM::LDMIA:
1882 Inst.setOpcode(ARM::RFEIA);
1884 case ARM::LDMIA_UPD:
1885 Inst.setOpcode(ARM::RFEIA_UPD);
1887 case ARM::LDMIB:
1888 Inst.setOpcode(ARM::RFEIB);
1890 case ARM::LDMIB_UPD:
1891 Inst.setOpcode(ARM::RFEIB_UPD);
1893 case ARM::STMDA:
1894 Inst.setOpcode(ARM::SRSDA);
1896 case ARM::STMDA_UPD:
1897 Inst.setOpcode(ARM::SRSDA_UPD);
1899 case ARM::STMDB:
1900 Inst.setOpcode(ARM::SRSDB);
1902 case ARM::STMDB_UPD:
1903 Inst.setOpcode(ARM::SRSDB_UPD);
1905 case ARM::STMIA:
1906 Inst.setOpcode(ARM::SRSIA);
1908 case ARM::STMIA_UPD:
1909 Inst.setOpcode(ARM::SRSIA_UPD);
1911 case ARM::STMIB:
1912 Inst.setOpcode(ARM::SRSIB);
1914 case ARM::STMIB_UPD:
1915 Inst.setOpcode(ARM::SRSIB_UPD);
1972 Inst.setOpcode(ARM::CPS3p);
1977 Inst.setOpcode(ARM::CPS2p);
1982 Inst.setOpcode(ARM::CPS1p);
1987 Inst.setOpcode(ARM::CPS1p);
2012 Inst.setOpcode(ARM::t2CPS3p);
2017 Inst.setOpcode(ARM::t2CPS2p);
2022 Inst.setOpcode(ARM::t2CPS1p);
2030 Inst.setOpcode(ARM::t2HINT);
2049 if (Inst.getOpcode() == ARM::t2MOVTi16)
2072 if (Inst.getOpcode() == ARM::MOVTi16)
2196 Inst.setOpcode(ARM::BLXi);
2244 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2245 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2246 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2247 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2248 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2249 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2250 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2251 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2252 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2256 case ARM::VLD2b16:
2257 case ARM::VLD2b32:
2258 case ARM::VLD2b8:
2259 case ARM::VLD2b16wb_fixed:
2260 case ARM::VLD2b16wb_register:
2261 case ARM::VLD2b32wb_fixed:
2262 case ARM::VLD2b32wb_register:
2263 case ARM::VLD2b8wb_fixed:
2264 case ARM::VLD2b8wb_register:
2275 case ARM::VLD3d8:
2276 case ARM::VLD3d16:
2277 case ARM::VLD3d32:
2278 case ARM::VLD3d8_UPD:
2279 case ARM::VLD3d16_UPD:
2280 case ARM::VLD3d32_UPD:
2281 case ARM::VLD4d8:
2282 case ARM::VLD4d16:
2283 case ARM::VLD4d32:
2284 case ARM::VLD4d8_UPD:
2285 case ARM::VLD4d16_UPD:
2286 case ARM::VLD4d32_UPD:
2290 case ARM::VLD3q8:
2291 case ARM::VLD3q16:
2292 case ARM::VLD3q32:
2293 case ARM::VLD3q8_UPD:
2294 case ARM::VLD3q16_UPD:
2295 case ARM::VLD3q32_UPD:
2296 case ARM::VLD4q8:
2297 case ARM::VLD4q16:
2298 case ARM::VLD4q32:
2299 case ARM::VLD4q8_UPD:
2300 case ARM::VLD4q16_UPD:
2301 case ARM::VLD4q32_UPD:
2310 case ARM::VLD3d8:
2311 case ARM::VLD3d16:
2312 case ARM::VLD3d32:
2313 case ARM::VLD3d8_UPD:
2314 case ARM::VLD3d16_UPD:
2315 case ARM::VLD3d32_UPD:
2316 case ARM::VLD4d8:
2317 case ARM::VLD4d16:
2318 case ARM::VLD4d32:
2319 case ARM::VLD4d8_UPD:
2320 case ARM::VLD4d16_UPD:
2321 case ARM::VLD4d32_UPD:
2325 case ARM::VLD3q8:
2326 case ARM::VLD3q16:
2327 case ARM::VLD3q32:
2328 case ARM::VLD3q8_UPD:
2329 case ARM::VLD3q16_UPD:
2330 case ARM::VLD3q32_UPD:
2331 case ARM::VLD4q8:
2332 case ARM::VLD4q16:
2333 case ARM::VLD4q32:
2334 case ARM::VLD4q8_UPD:
2335 case ARM::VLD4q16_UPD:
2336 case ARM::VLD4q32_UPD:
2346 case ARM::VLD4d8:
2347 case ARM::VLD4d16:
2348 case ARM::VLD4d32:
2349 case ARM::VLD4d8_UPD:
2350 case ARM::VLD4d16_UPD:
2351 case ARM::VLD4d32_UPD:
2355 case ARM::VLD4q8:
2356 case ARM::VLD4q16:
2357 case ARM::VLD4q32:
2358 case ARM::VLD4q8_UPD:
2359 case ARM::VLD4q16_UPD:
2360 case ARM::VLD4q32_UPD:
2370 case ARM::VLD1d8wb_fixed:
2371 case ARM::VLD1d16wb_fixed:
2372 case ARM::VLD1d32wb_fixed:
2373 case ARM::VLD1d64wb_fixed:
2374 case ARM::VLD1d8wb_register:
2375 case ARM::VLD1d16wb_register:
2376 case ARM::VLD1d32wb_register:
2377 case ARM::VLD1d64wb_register:
2378 case ARM::VLD1q8wb_fixed:
2379 case ARM::VLD1q16wb_fixed:
2380 case ARM::VLD1q32wb_fixed:
2381 case ARM::VLD1q64wb_fixed:
2382 case ARM::VLD1q8wb_register:
2383 case ARM::VLD1q16wb_register:
2384 case ARM::VLD1q32wb_register:
2385 case ARM::VLD1q64wb_register:
2386 case ARM::VLD1d8Twb_fixed:
2387 case ARM::VLD1d8Twb_register:
2388 case ARM::VLD1d16Twb_fixed:
2389 case ARM::VLD1d16Twb_register:
2390 case ARM::VLD1d32Twb_fixed:
2391 case ARM::VLD1d32Twb_register:
2392 case ARM::VLD1d64Twb_fixed:
2393 case ARM::VLD1d64Twb_register:
2394 case ARM::VLD1d8Qwb_fixed:
2395 case ARM::VLD1d8Qwb_register:
2396 case ARM::VLD1d16Qwb_fixed:
2397 case ARM::VLD1d16Qwb_register:
2398 case ARM::VLD1d32Qwb_fixed:
2399 case ARM::VLD1d32Qwb_register:
2400 case ARM::VLD1d64Qwb_fixed:
2401 case ARM::VLD1d64Qwb_register:
2402 case ARM::VLD2d8wb_fixed:
2403 case ARM::VLD2d16wb_fixed:
2404 case ARM::VLD2d32wb_fixed:
2405 case ARM::VLD2q8wb_fixed:
2406 case ARM::VLD2q16wb_fixed:
2407 case ARM::VLD2q32wb_fixed:
2408 case ARM::VLD2d8wb_register:
2409 case ARM::VLD2d16wb_register:
2410 case ARM::VLD2d32wb_register:
2411 case ARM::VLD2q8wb_register:
2412 case ARM::VLD2q16wb_register:
2413 case ARM::VLD2q32wb_register:
2414 case ARM::VLD2b8wb_fixed:
2415 case ARM::VLD2b16wb_fixed:
2416 case ARM::VLD2b32wb_fixed:
2417 case ARM::VLD2b8wb_register:
2418 case ARM::VLD2b16wb_register:
2419 case ARM::VLD2b32wb_register:
2422 case ARM::VLD3d8_UPD:
2423 case ARM::VLD3d16_UPD:
2424 case ARM::VLD3d32_UPD:
2425 case ARM::VLD3q8_UPD:
2426 case ARM::VLD3q16_UPD:
2427 case ARM::VLD3q32_UPD:
2428 case ARM::VLD4d8_UPD:
2429 case ARM::VLD4d16_UPD:
2430 case ARM::VLD4d32_UPD:
2431 case ARM::VLD4q8_UPD:
2432 case ARM::VLD4q16_UPD:
2433 case ARM::VLD4q32_UPD:
2459 case ARM::VLD1d8wb_fixed:
2460 case ARM::VLD1d16wb_fixed:
2461 case ARM::VLD1d32wb_fixed:
2462 case ARM::VLD1d64wb_fixed:
2463 case ARM::VLD1d8Twb_fixed:
2464 case ARM::VLD1d16Twb_fixed:
2465 case ARM::VLD1d32Twb_fixed:
2466 case ARM::VLD1d64Twb_fixed:
2467 case ARM::VLD1d8Qwb_fixed:
2468 case ARM::VLD1d16Qwb_fixed:
2469 case ARM::VLD1d32Qwb_fixed:
2470 case ARM::VLD1d64Qwb_fixed:
2471 case ARM::VLD1d8wb_register:
2472 case ARM::VLD1d16wb_register:
2473 case ARM::VLD1d32wb_register:
2474 case ARM::VLD1d64wb_register:
2475 case ARM::VLD1q8wb_fixed:
2476 case ARM::VLD1q16wb_fixed:
2477 case ARM::VLD1q32wb_fixed:
2478 case ARM::VLD1q64wb_fixed:
2479 case ARM::VLD1q8wb_register:
2480 case ARM::VLD1q16wb_register:
2481 case ARM::VLD1q32wb_register:
2482 case ARM::VLD1q64wb_register:
2490 case ARM::VLD2d8wb_fixed:
2491 case ARM::VLD2d16wb_fixed:
2492 case ARM::VLD2d32wb_fixed:
2493 case ARM::VLD2b8wb_fixed:
2494 case ARM::VLD2b16wb_fixed:
2495 case ARM::VLD2b32wb_fixed:
2496 case ARM::VLD2q8wb_fixed:
2497 case ARM::VLD2q16wb_fixed:
2498 case ARM::VLD2q32wb_fixed:
2569 case ARM::VST1d8wb_fixed:
2570 case ARM::VST1d16wb_fixed:
2571 case ARM::VST1d32wb_fixed:
2572 case ARM::VST1d64wb_fixed:
2573 case ARM::VST1d8wb_register:
2574 case ARM::VST1d16wb_register:
2575 case ARM::VST1d32wb_register:
2576 case ARM::VST1d64wb_register:
2577 case ARM::VST1q8wb_fixed:
2578 case ARM::VST1q16wb_fixed:
2579 case ARM::VST1q32wb_fixed:
2580 case ARM::VST1q64wb_fixed:
2581 case ARM::VST1q8wb_register:
2582 case ARM::VST1q16wb_register:
2583 case ARM::VST1q32wb_register:
2584 case ARM::VST1q64wb_register:
2585 case ARM::VST1d8Twb_fixed:
2586 case ARM::VST1d16Twb_fixed:
2587 case ARM::VST1d32Twb_fixed:
2588 case ARM::VST1d64Twb_fixed:
2589 case ARM::VST1d8Twb_register:
2590 case ARM::VST1d16Twb_register:
2591 case ARM::VST1d32Twb_register:
2592 case ARM::VST1d64Twb_register:
2593 case ARM::VST1d8Qwb_fixed:
2594 case ARM::VST1d16Qwb_fixed:
2595 case ARM::VST1d32Qwb_fixed:
2596 case ARM::VST1d64Qwb_fixed:
2597 case ARM::VST1d8Qwb_register:
2598 case ARM::VST1d16Qwb_register:
2599 case ARM::VST1d32Qwb_register:
2600 case ARM::VST1d64Qwb_register:
2601 case ARM::VST2d8wb_fixed:
2602 case ARM::VST2d16wb_fixed:
2603 case ARM::VST2d32wb_fixed:
2604 case ARM::VST2d8wb_register:
2605 case ARM::VST2d16wb_register:
2606 case ARM::VST2d32wb_register:
2607 case ARM::VST2q8wb_fixed:
2608 case ARM::VST2q16wb_fixed:
2609 case ARM::VST2q32wb_fixed:
2610 case ARM::VST2q8wb_register:
2611 case ARM::VST2q16wb_register:
2612 case ARM::VST2q32wb_register:
2613 case ARM::VST2b8wb_fixed:
2614 case ARM::VST2b16wb_fixed:
2615 case ARM::VST2b32wb_fixed:
2616 case ARM::VST2b8wb_register:
2617 case ARM::VST2b16wb_register:
2618 case ARM::VST2b32wb_register:
2623 case ARM::VST3d8_UPD:
2624 case ARM::VST3d16_UPD:
2625 case ARM::VST3d32_UPD:
2626 case ARM::VST3q8_UPD:
2627 case ARM::VST3q16_UPD:
2628 case ARM::VST3q32_UPD:
2629 case ARM::VST4d8_UPD:
2630 case ARM::VST4d16_UPD:
2631 case ARM::VST4d32_UPD:
2632 case ARM::VST4q8_UPD:
2633 case ARM::VST4q16_UPD:
2634 case ARM::VST4q32_UPD:
2656 case ARM::VST1d8wb_fixed:
2657 case ARM::VST1d16wb_fixed:
2658 case ARM::VST1d32wb_fixed:
2659 case ARM::VST1d64wb_fixed:
2660 case ARM::VST1q8wb_fixed:
2661 case ARM::VST1q16wb_fixed:
2662 case ARM::VST1q32wb_fixed:
2663 case ARM::VST1q64wb_fixed:
2664 case ARM::VST1d8Twb_fixed:
2665 case ARM::VST1d16Twb_fixed:
2666 case ARM::VST1d32Twb_fixed:
2667 case ARM::VST1d64Twb_fixed:
2668 case ARM::VST1d8Qwb_fixed:
2669 case ARM::VST1d16Qwb_fixed:
2670 case ARM::VST1d32Qwb_fixed:
2671 case ARM::VST1d64Qwb_fixed:
2672 case ARM::VST2d8wb_fixed:
2673 case ARM::VST2d16wb_fixed:
2674 case ARM::VST2d32wb_fixed:
2675 case ARM::VST2q8wb_fixed:
2676 case ARM::VST2q16wb_fixed:
2677 case ARM::VST2q32wb_fixed:
2678 case ARM::VST2b8wb_fixed:
2679 case ARM::VST2b16wb_fixed:
2680 case ARM::VST2b32wb_fixed:
2687 case ARM::VST1q16:
2688 case ARM::VST1q32:
2689 case ARM::VST1q64:
2690 case ARM::VST1q8:
2691 case ARM::VST1q16wb_fixed:
2692 case ARM::VST1q16wb_register:
2693 case ARM::VST1q32wb_fixed:
2694 case ARM::VST1q32wb_register:
2695 case ARM::VST1q64wb_fixed:
2696 case ARM::VST1q64wb_register:
2697 case ARM::VST1q8wb_fixed:
2698 case ARM::VST1q8wb_register:
2699 case ARM::VST2d16:
2700 case ARM::VST2d32:
2701 case ARM::VST2d8:
2702 case ARM::VST2d16wb_fixed:
2703 case ARM::VST2d16wb_register:
2704 case ARM::VST2d32wb_fixed:
2705 case ARM::VST2d32wb_register:
2706 case ARM::VST2d8wb_fixed:
2707 case ARM::VST2d8wb_register:
2711 case ARM::VST2b16:
2712 case ARM::VST2b32:
2713 case ARM::VST2b8:
2714 case ARM::VST2b16wb_fixed:
2715 case ARM::VST2b16wb_register:
2716 case ARM::VST2b32wb_fixed:
2717 case ARM::VST2b32wb_register:
2718 case ARM::VST2b8wb_fixed:
2719 case ARM::VST2b8wb_register:
2730 case ARM::VST3d8:
2731 case ARM::VST3d16:
2732 case ARM::VST3d32:
2733 case ARM::VST3d8_UPD:
2734 case ARM::VST3d16_UPD:
2735 case ARM::VST3d32_UPD:
2736 case ARM::VST4d8:
2737 case ARM::VST4d16:
2738 case ARM::VST4d32:
2739 case ARM::VST4d8_UPD:
2740 case ARM::VST4d16_UPD:
2741 case ARM::VST4d32_UPD:
2745 case ARM::VST3q8:
2746 case ARM::VST3q16:
2747 case ARM::VST3q32:
2748 case ARM::VST3q8_UPD:
2749 case ARM::VST3q16_UPD:
2750 case ARM::VST3q32_UPD:
2751 case ARM::VST4q8:
2752 case ARM::VST4q16:
2753 case ARM::VST4q32:
2754 case ARM::VST4q8_UPD:
2755 case ARM::VST4q16_UPD:
2756 case ARM::VST4q32_UPD:
2766 case ARM::VST3d8:
2767 case ARM::VST3d16:
2768 case ARM::VST3d32:
2769 case ARM::VST3d8_UPD:
2770 case ARM::VST3d16_UPD:
2771 case ARM::VST3d32_UPD:
2772 case ARM::VST4d8:
2773 case ARM::VST4d16:
2774 case ARM::VST4d32:
2775 case ARM::VST4d8_UPD:
2776 case ARM::VST4d16_UPD:
2777 case ARM::VST4d32_UPD:
2781 case ARM::VST3q8:
2782 case ARM::VST3q16:
2783 case ARM::VST3q32:
2784 case ARM::VST3q8_UPD:
2785 case ARM::VST3q16_UPD:
2786 case ARM::VST3q32_UPD:
2787 case ARM::VST4q8:
2788 case ARM::VST4q16:
2789 case ARM::VST4q32:
2790 case ARM::VST4q8_UPD:
2791 case ARM::VST4q16_UPD:
2792 case ARM::VST4q32_UPD:
2802 case ARM::VST4d8:
2803 case ARM::VST4d16:
2804 case ARM::VST4d32:
2805 case ARM::VST4d8_UPD:
2806 case ARM::VST4d16_UPD:
2807 case ARM::VST4d32_UPD:
2811 case ARM::VST4q8:
2812 case ARM::VST4q16:
2813 case ARM::VST4q32:
2814 case ARM::VST4q8_UPD:
2815 case ARM::VST4q16_UPD:
2816 case ARM::VST4q32_UPD:
2843 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2844 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2845 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2846 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2887 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2888 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2889 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2890 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2894 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2895 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2896 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2897 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3036 case ARM::VORRiv4i16:
3037 case ARM::VORRiv2i32:
3038 case ARM::VBICiv4i16:
3039 case ARM::VBICiv2i32:
3043 case ARM::VORRiv8i16:
3044 case ARM::VORRiv4i32:
3045 case ARM::VBICiv8i16:
3046 case ARM::VBICiv4i32:
3120 case ARM::VTBL2:
3121 case ARM::VTBX2:
3149 case ARM::tADR:
3151 case ARM::tADDrSPi:
3152 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3225 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3241 case ARM::t2STRHs:
3242 case ARM::t2STRBs:
3243 case ARM::t2STRs:
3268 case ARM::t2LDRBs:
3269 Inst.setOpcode(ARM::t2LDRBpci);
3271 case ARM::t2LDRHs:
3272 Inst.setOpcode(ARM::t2LDRHpci);
3274 case ARM::t2LDRSHs:
3275 Inst.setOpcode(ARM::t2LDRSHpci);
3277 case ARM::t2LDRSBs:
3278 Inst.setOpcode(ARM::t2LDRSBpci);
3280 case ARM::t2LDRs:
3281 Inst.setOpcode(ARM::t2LDRpci);
3283 case ARM::t2PLDs:
3284 Inst.setOpcode(ARM::t2PLDpci);
3286 case ARM::t2PLIs:
3287 Inst.setOpcode(ARM::t2PLIpci);
3298 case ARM::t2LDRSHs:
3300 case ARM::t2LDRHs:
3304 Inst.setOpcode(ARM::t2PLDWs);
3312 case ARM::t2PLDs:
3313 case ARM::t2PLDWs:
3314 case ARM::t2PLIs:
3343 case ARM::t2LDRi8:
3344 Inst.setOpcode(ARM::t2LDRpci);
3346 case ARM::t2LDRBi8:
3347 Inst.setOpcode(ARM::t2LDRBpci);
3349 case ARM::t2LDRSBi8:
3350 Inst.setOpcode(ARM::t2LDRSBpci);
3352 case ARM::t2LDRHi8:
3353 Inst.setOpcode(ARM::t2LDRHpci);
3355 case ARM::t2LDRSHi8:
3356 Inst.setOpcode(ARM::t2LDRSHpci);
3358 case ARM::t2PLDi8:
3359 Inst.setOpcode(ARM::t2PLDpci);
3361 case ARM::t2PLIi8:
3362 Inst.setOpcode(ARM::t2PLIpci);
3372 case ARM::t2LDRSHi8:
3380 case ARM::t2PLDi8:
3381 case ARM::t2PLIi8:
3382 case ARM::t2PLDWi8:
3405 case ARM::t2LDRi12:
3406 Inst.setOpcode(ARM::t2LDRpci);
3408 case ARM::t2LDRHi12:
3409 Inst.setOpcode(ARM::t2LDRHpci);
3411 case ARM::t2LDRSHi12:
3412 Inst.setOpcode(ARM::t2LDRSHpci);
3414 case ARM::t2LDRBi12:
3415 Inst.setOpcode(ARM::t2LDRBpci);
3417 case ARM::t2LDRSBi12:
3418 Inst.setOpcode(ARM::t2LDRSBpci);
3420 case ARM::t2PLDi12:
3421 Inst.setOpcode(ARM::t2PLDpci);
3423 case ARM::t2PLIi12:
3424 Inst.setOpcode(ARM::t2PLIpci);
3434 case ARM::t2LDRSHi12:
3436 case ARM::t2LDRHi12:
3437 Inst.setOpcode(ARM::t2PLDi12);
3445 case ARM::t2PLDi12:
3446 case ARM::t2PLDWi12:
3447 case ARM::t2PLIi12:
3470 case ARM::t2LDRT:
3471 Inst.setOpcode(ARM::t2LDRpci);
3473 case ARM::t2LDRBT:
3474 Inst.setOpcode(ARM::t2LDRBpci);
3476 case ARM::t2LDRHT:
3477 Inst.setOpcode(ARM::t2LDRHpci);
3479 case ARM::t2LDRSBT:
3480 Inst.setOpcode(ARM::t2LDRSBpci);
3482 case ARM::t2LDRSHT:
3483 Inst.setOpcode(ARM::t2LDRSHpci);
3508 case ARM::t2LDRBpci:
3509 case ARM::t2LDRHpci:
3510 Inst.setOpcode(ARM::t2PLDpci);
3512 case ARM::t2LDRSBpci:
3513 Inst.setOpcode(ARM::t2PLIpci);
3515 case ARM::t2LDRSHpci:
3523 case ARM::t2PLDpci:
3524 case ARM::t2PLIpci:
3609 case ARM::t2STRT:
3610 case ARM::t2STRBT:
3611 case ARM::t2STRHT:
3612 case ARM::t2STRi8:
3613 case ARM::t2STRHi8:
3614 case ARM::t2STRBi8:
3624 case ARM::t2LDRT:
3625 case ARM::t2LDRBT:
3626 case ARM::t2LDRHT:
3627 case ARM::t2LDRSBT:
3628 case ARM::t2LDRSHT:
3629 case ARM::t2STRT:
3630 case ARM::t2STRBT:
3631 case ARM::t2STRHT:
3659 case ARM::t2LDR_PRE:
3660 case ARM::t2LDR_POST:
3661 Inst.setOpcode(ARM::t2LDRpci);
3663 case ARM::t2LDRB_PRE:
3664 case ARM::t2LDRB_POST:
3665 Inst.setOpcode(ARM::t2LDRBpci);
3667 case ARM::t2LDRH_PRE:
3668 case ARM::t2LDRH_POST:
3669 Inst.setOpcode(ARM::t2LDRHpci);
3671 case ARM::t2LDRSB_PRE:
3672 case ARM::t2LDRSB_POST:
3674 Inst.setOpcode(ARM::t2PLIpci);
3676 Inst.setOpcode(ARM::t2LDRSBpci);
3678 case ARM::t2LDRSH_PRE:
3679 case ARM::t2LDRSH_POST:
3680 Inst.setOpcode(ARM::t2LDRSHpci);
3716 case ARM::t2STRi12:
3717 case ARM::t2STRBi12:
3718 case ARM::t2STRHi12:
3737 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3738 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3748 if (Inst.getOpcode() == ARM::tADDrSP) {
3754 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3757 } else if (Inst.getOpcode() == ARM::tADDspr) {
3760 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3761 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3824 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3839 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3859 Inst.setOpcode(ARM::t2DSB);
3862 Inst.setOpcode(ARM::t2DMB);
3865 Inst.setOpcode(ARM::t2ISB);
4889 Inst.setOpcode(ARM::VMOVv2f32);
4919 Inst.setOpcode(ARM::VMOVv4f32);