Lines Matching refs:ARM
1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
10 // This file defines an instruction selector for the ARM target.
15 #include "ARM.h"
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
77 return "ARM Instruction Selection";
136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
208 /// ARM.
246 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
409 /// least on current ARM implementations) which should be avoidded.
435 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
1092 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1093 (RHSR && RHSR->getReg() == ARM::SP))
1157 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1158 (RHSR && RHSR->getReg() == ARM::SP)) {
1218 (LHSR && LHSR->getReg() == ARM::SP)) {
1461 Opcode = ARM::LDR_PRE_IMM;
1465 Opcode = ARM::LDR_POST_IMM;
1469 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1476 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1477 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1482 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1488 Opcode = ARM::LDRB_PRE_IMM;
1492 Opcode = ARM::LDRB_POST_IMM;
1495 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1501 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1536 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1540 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1542 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1547 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1549 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1573 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1574 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1575 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1584 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1585 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1586 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1594 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1595 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1596 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1604 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1605 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1606 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1616 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1617 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1618 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1619 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1620 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1630 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1631 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1632 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1633 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1634 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1644 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1645 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1646 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1647 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1648 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1680 case ARM::VLD1d8wb_fixed : return true;
1681 case ARM::VLD1d16wb_fixed : return true;
1682 case ARM::VLD1d64Qwb_fixed : return true;
1683 case ARM::VLD1d32wb_fixed : return true;
1684 case ARM::VLD1d64wb_fixed : return true;
1685 case ARM::VLD1d64TPseudoWB_fixed : return true;
1686 case ARM::VLD1d64QPseudoWB_fixed : return true;
1687 case ARM::VLD1q8wb_fixed : return true;
1688 case ARM::VLD1q16wb_fixed : return true;
1689 case ARM::VLD1q32wb_fixed : return true;
1690 case ARM::VLD1q64wb_fixed : return true;
1691 case ARM::VLD2d8wb_fixed : return true;
1692 case ARM::VLD2d16wb_fixed : return true;
1693 case ARM::VLD2d32wb_fixed : return true;
1694 case ARM::VLD2q8PseudoWB_fixed : return true;
1695 case ARM::VLD2q16PseudoWB_fixed : return true;
1696 case ARM::VLD2q32PseudoWB_fixed : return true;
1697 case ARM::VLD2DUPd8wb_fixed : return true;
1698 case ARM::VLD2DUPd16wb_fixed : return true;
1699 case ARM::VLD2DUPd32wb_fixed : return true;
1707 case ARM::VST1d8wb_fixed : return true;
1708 case ARM::VST1d16wb_fixed : return true;
1709 case ARM::VST1d32wb_fixed : return true;
1710 case ARM::VST1d64wb_fixed : return true;
1711 case ARM::VST1q8wb_fixed : return true;
1712 case ARM::VST1q16wb_fixed : return true;
1713 case ARM::VST1q32wb_fixed : return true;
1714 case ARM::VST1q64wb_fixed : return true;
1715 case ARM::VST1d64TPseudoWB_fixed : return true;
1716 case ARM::VST1d64QPseudoWB_fixed : return true;
1717 case ARM::VST2d8wb_fixed : return true;
1718 case ARM::VST2d16wb_fixed : return true;
1719 case ARM::VST2d32wb_fixed : return true;
1720 case ARM::VST2q8PseudoWB_fixed : return true;
1721 case ARM::VST2q16PseudoWB_fixed : return true;
1722 case ARM::VST2q32PseudoWB_fixed : return true;
1733 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1734 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1735 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1736 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1737 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1738 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1739 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1740 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1741 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1742 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1743 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1744 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1746 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1747 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1748 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1749 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1750 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1751 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1752 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1753 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1754 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1755 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1757 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1758 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1759 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1760 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1761 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1762 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1764 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1765 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1766 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1767 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1768 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1769 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1771 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1772 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1773 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1898 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1899 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1900 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
2163 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2164 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2165 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2247 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2248 unsigned SubIdx = ARM::dsub_0;
2297 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2298 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2323 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2330 // ARM models shift instructions as MOVsi with shifter operand.
2337 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2381 /// ARM instruction selection detects the latter and matches it to
2382 /// ARM::ABS or ARM::t2ABS machine node.
2405 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2506 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2516 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2534 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2537 ARM::t2ADDri : ARM::ADDri);
2568 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2571 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2584 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2587 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2606 ? ARM::t2MOVTi16
2607 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2634 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2643 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2649 ARM::UMULL : ARM::UMULLv5,
2659 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2665 ARM::SMULL : ARM::SMULLv5,
2674 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2681 ARM::UMLAL : ARM::UMLALv5,
2690 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2697 ARM::SMLAL : ARM::SMLALv5,
2726 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2756 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2757 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2760 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2761 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2762 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2764 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2776 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2777 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2780 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2781 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2782 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2784 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2796 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2797 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2799 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2800 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2801 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2803 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2827 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2828 ARM::VLD2DUPd32 };
2833 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2834 ARM::VLD3DUPd16Pseudo,
2835 ARM::VLD3DUPd32Pseudo };
2840 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2841 ARM::VLD4DUPd16Pseudo,
2842 ARM::VLD4DUPd32Pseudo };
2847 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2848 ARM::VLD2DUPd16wb_fixed,
2849 ARM::VLD2DUPd32wb_fixed };
2854 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2855 ARM::VLD3DUPd16Pseudo_UPD,
2856 ARM::VLD3DUPd32Pseudo_UPD };
2861 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2862 ARM::VLD4DUPd16Pseudo_UPD,
2863 ARM::VLD4DUPd32Pseudo_UPD };
2868 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2869 ARM::VLD1d16wb_fixed,
2870 ARM::VLD1d32wb_fixed,
2871 ARM::VLD1d64wb_fixed };
2872 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2873 ARM::VLD1q16wb_fixed,
2874 ARM::VLD1q32wb_fixed,
2875 ARM::VLD1q64wb_fixed };
2880 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2881 ARM::VLD2d16wb_fixed,
2882 ARM::VLD2d32wb_fixed,
2883 ARM::VLD1q64wb_fixed};
2884 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2885 ARM::VLD2q16PseudoWB_fixed,
2886 ARM::VLD2q32PseudoWB_fixed };
2891 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2892 ARM::VLD3d16Pseudo_UPD,
2893 ARM::VLD3d32Pseudo_UPD,
2894 ARM::VLD1d64TPseudoWB_fixed};
2895 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2896 ARM::VLD3q16Pseudo_UPD,
2897 ARM::VLD3q32Pseudo_UPD };
2898 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2899 ARM::VLD3q16oddPseudo_UPD,
2900 ARM::VLD3q32oddPseudo_UPD };
2905 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2906 ARM::VLD4d16Pseudo_UPD,
2907 ARM::VLD4d32Pseudo_UPD,
2908 ARM::VLD1d64QPseudoWB_fixed};
2909 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2910 ARM::VLD4q16Pseudo_UPD,
2911 ARM::VLD4q32Pseudo_UPD };
2912 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2913 ARM::VLD4q16oddPseudo_UPD,
2914 ARM::VLD4q32oddPseudo_UPD };
2919 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2920 ARM::VLD2LNd16Pseudo_UPD,
2921 ARM::VLD2LNd32Pseudo_UPD };
2922 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2923 ARM::VLD2LNq32Pseudo_UPD };
2928 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2929 ARM::VLD3LNd16Pseudo_UPD,
2930 ARM::VLD3LNd32Pseudo_UPD };
2931 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2932 ARM::VLD3LNq32Pseudo_UPD };
2937 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2938 ARM::VLD4LNd16Pseudo_UPD,
2939 ARM::VLD4LNd32Pseudo_UPD };
2940 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2941 ARM::VLD4LNq32Pseudo_UPD };
2946 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2947 ARM::VST1d16wb_fixed,
2948 ARM::VST1d32wb_fixed,
2949 ARM::VST1d64wb_fixed };
2950 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2951 ARM::VST1q16wb_fixed,
2952 ARM::VST1q32wb_fixed,
2953 ARM::VST1q64wb_fixed };
2958 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2959 ARM::VST2d16wb_fixed,
2960 ARM::VST2d32wb_fixed,
2961 ARM::VST1q64wb_fixed};
2962 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2963 ARM::VST2q16PseudoWB_fixed,
2964 ARM::VST2q32PseudoWB_fixed };
2969 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2970 ARM::VST3d16Pseudo_UPD,
2971 ARM::VST3d32Pseudo_UPD,
2972 ARM::VST1d64TPseudoWB_fixed};
2973 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2974 ARM::VST3q16Pseudo_UPD,
2975 ARM::VST3q32Pseudo_UPD };
2976 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2977 ARM::VST3q16oddPseudo_UPD,
2978 ARM::VST3q32oddPseudo_UPD };
2983 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2984 ARM::VST4d16Pseudo_UPD,
2985 ARM::VST4d32Pseudo_UPD,
2986 ARM::VST1d64QPseudoWB_fixed};
2987 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2988 ARM::VST4q16Pseudo_UPD,
2989 ARM::VST4q32Pseudo_UPD };
2990 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2991 ARM::VST4q16oddPseudo_UPD,
2992 ARM::VST4q32oddPseudo_UPD };
2997 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2998 ARM::VST2LNd16Pseudo_UPD,
2999 ARM::VST2LNd32Pseudo_UPD };
3000 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3001 ARM::VST2LNq32Pseudo_UPD };
3006 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
3007 ARM::VST3LNd16Pseudo_UPD,
3008 ARM::VST3LNd32Pseudo_UPD };
3009 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3010 ARM::VST3LNq32Pseudo_UPD };
3015 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3016 ARM::VST4LNd16Pseudo_UPD,
3017 ARM::VST4LNd32Pseudo_UPD };
3018 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3019 ARM::VST4LNq32Pseudo_UPD };
3036 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD;
3066 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3078 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3114 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD;
3126 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3127 ARM::VLD1d32, ARM::VLD1d64 };
3128 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3129 ARM::VLD1q32, ARM::VLD1q64};
3134 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3135 ARM::VLD2d32, ARM::VLD1q64 };
3136 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3137 ARM::VLD2q32Pseudo };
3142 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3143 ARM::VLD3d16Pseudo,
3144 ARM::VLD3d32Pseudo,
3145 ARM::VLD1d64TPseudo };
3146 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3147 ARM::VLD3q16Pseudo_UPD,
3148 ARM::VLD3q32Pseudo_UPD };
3149 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3150 ARM::VLD3q16oddPseudo,
3151 ARM::VLD3q32oddPseudo };
3156 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3157 ARM::VLD4d16Pseudo,
3158 ARM::VLD4d32Pseudo,
3159 ARM::VLD1d64QPseudo };
3160 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3161 ARM::VLD4q16Pseudo_UPD,
3162 ARM::VLD4q32Pseudo_UPD };
3163 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3164 ARM::VLD4q16oddPseudo,
3165 ARM::VLD4q32oddPseudo };
3170 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3171 ARM::VLD2LNd16Pseudo,
3172 ARM::VLD2LNd32Pseudo };
3173 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3174 ARM::VLD2LNq32Pseudo };
3179 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3180 ARM::VLD3LNd16Pseudo,
3181 ARM::VLD3LNd32Pseudo };
3182 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3183 ARM::VLD3LNq32Pseudo };
3188 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3189 ARM::VLD4LNd16Pseudo,
3190 ARM::VLD4LNd32Pseudo };
3191 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3192 ARM::VLD4LNq32Pseudo };
3197 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3198 ARM::VST1d32, ARM::VST1d64 };
3199 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3200 ARM::VST1q32, ARM::VST1q64 };
3205 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3206 ARM::VST2d32, ARM::VST1q64 };
3207 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3208 ARM::VST2q32Pseudo };
3213 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3214 ARM::VST3d16Pseudo,
3215 ARM::VST3d32Pseudo,
3216 ARM::VST1d64TPseudo };
3217 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3218 ARM::VST3q16Pseudo_UPD,
3219 ARM::VST3q32Pseudo_UPD };
3220 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3221 ARM::VST3q16oddPseudo,
3222 ARM::VST3q32oddPseudo };
3227 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3228 ARM::VST4d16Pseudo,
3229 ARM::VST4d32Pseudo,
3230 ARM::VST1d64QPseudo };
3231 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3232 ARM::VST4q16Pseudo_UPD,
3233 ARM::VST4q32Pseudo_UPD };
3234 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3235 ARM::VST4q16oddPseudo,
3236 ARM::VST4q32oddPseudo };
3241 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3242 ARM::VST2LNd16Pseudo,
3243 ARM::VST2LNd32Pseudo };
3244 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3245 ARM::VST2LNq32Pseudo };
3250 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3251 ARM::VST3LNd16Pseudo,
3252 ARM::VST3LNd32Pseudo };
3253 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3254 ARM::VST3LNq32Pseudo };
3259 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3260 ARM::VST4LNd16Pseudo,
3261 ARM::VST4LNd32Pseudo };
3262 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3263 ARM::VST4LNq32Pseudo };
3277 return SelectVTBL(N, false, 2, ARM::VTBL2);
3279 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3281 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3284 return SelectVTBL(N, true, 2, ARM::VTBX2);
3286 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3288 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3302 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3318 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3326 return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_LOAD_I64);
3332 return SelectAtomic(N, 0, 0, 0, ARM::ATOMIC_STORE_I64);
3338 ARM::ATOMIC_LOAD_ADD_I8,
3339 ARM::ATOMIC_LOAD_ADD_I16,
3340 ARM::ATOMIC_LOAD_ADD_I32,
3341 ARM::ATOMIC_LOAD_ADD_I64);
3344 ARM::ATOMIC_LOAD_SUB_I8,
3345 ARM::ATOMIC_LOAD_SUB_I16,
3346 ARM::ATOMIC_LOAD_SUB_I32,
3347 ARM::ATOMIC_LOAD_SUB_I64);
3350 ARM::ATOMIC_LOAD_AND_I8,
3351 ARM::ATOMIC_LOAD_AND_I16,
3352 ARM::ATOMIC_LOAD_AND_I32,
3353 ARM::ATOMIC_LOAD_AND_I64);
3356 ARM::ATOMIC_LOAD_OR_I8,
3357 ARM::ATOMIC_LOAD_OR_I16,
3358 ARM::ATOMIC_LOAD_OR_I32,
3359 ARM::ATOMIC_LOAD_OR_I64);
3362 ARM::ATOMIC_LOAD_XOR_I8,
3363 ARM::ATOMIC_LOAD_XOR_I16,
3364 ARM::ATOMIC_LOAD_XOR_I32,
3365 ARM::ATOMIC_LOAD_XOR_I64);
3368 ARM::ATOMIC_LOAD_NAND_I8,
3369 ARM::ATOMIC_LOAD_NAND_I16,
3370 ARM::ATOMIC_LOAD_NAND_I32,
3371 ARM::ATOMIC_LOAD_NAND_I64);
3374 ARM::ATOMIC_LOAD_MIN_I8,
3375 ARM::ATOMIC_LOAD_MIN_I16,
3376 ARM::ATOMIC_LOAD_MIN_I32,
3377 ARM::ATOMIC_LOAD_MIN_I64);
3380 ARM::ATOMIC_LOAD_MAX_I8,
3381 ARM::ATOMIC_LOAD_MAX_I16,
3382 ARM::ATOMIC_LOAD_MAX_I32,
3383 ARM::ATOMIC_LOAD_MAX_I64);
3386 ARM::ATOMIC_LOAD_UMIN_I8,
3387 ARM::ATOMIC_LOAD_UMIN_I16,
3388 ARM::ATOMIC_LOAD_UMIN_I32,
3389 ARM::ATOMIC_LOAD_UMIN_I64);
3392 ARM::ATOMIC_LOAD_UMAX_I8,
3393 ARM::ATOMIC_LOAD_UMAX_I16,
3394 ARM::ATOMIC_LOAD_UMAX_I32,
3395 ARM::ATOMIC_LOAD_UMAX_I64);
3398 ARM::ATOMIC_SWAP_I8,
3399 ARM::ATOMIC_SWAP_I16,
3400 ARM::ATOMIC_SWAP_I32,
3401 ARM::ATOMIC_SWAP_I64);
3404 ARM::ATOMIC_CMP_SWAP_I8,
3405 ARM::ATOMIC_CMP_SWAP_I16,
3406 ARM::ATOMIC_CMP_SWAP_I32,
3407 ARM::ATOMIC_CMP_SWAP_I64);
3420 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3473 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3490 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3499 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3501 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3527 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3543 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3571 // Require the address to be in a register. That is safe for all ARM
3579 /// ARM-specific DAG, ready for instruction scheduling.