Lines Matching refs:ARM
15 #include "ARM.h"
39 NopInst.setOpcode(ARM::tHINT);
81 if (MBBI->getOpcode() == ARM::t2IT) {
119 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
122 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
142 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
143 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
144 RC == &ARM::GPRnopcRegClass) {
145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
151 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
156 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
158 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
159 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
160 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
184 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
185 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
186 RC == &ARM::GPRnopcRegClass) {
187 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
192 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
197 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
199 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
200 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
201 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
219 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
230 if (DestReg != ARM::SP && DestReg != BaseReg &&
236 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
242 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
251 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
257 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
270 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
272 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
274 BaseReg = ARM::SP;
279 if (BaseReg == ARM::SP) {
281 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
283 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
291 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
303 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
304 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
308 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
337 case ARM::t2LDRi12: return ARM::t2LDRi8;
338 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
339 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
340 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
341 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
342 case ARM::t2STRi12: return ARM::t2STRi8;
343 case ARM::t2STRBi12: return ARM::t2STRBi8;
344 case ARM::t2STRHi12: return ARM::t2STRHi8;
345 case ARM::t2PLDi12: return ARM::t2PLDi8;
347 case ARM::t2LDRi8:
348 case ARM::t2LDRHi8:
349 case ARM::t2LDRBi8:
350 case ARM::t2LDRSHi8:
351 case ARM::t2LDRSBi8:
352 case ARM::t2STRi8:
353 case ARM::t2STRBi8:
354 case ARM::t2STRHi8:
355 case ARM::t2PLDi8:
369 case ARM::t2LDRi8: return ARM::t2LDRi12;
370 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
371 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
372 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
373 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
374 case ARM::t2STRi8: return ARM::t2STRi12;
375 case ARM::t2STRBi8: return ARM::t2STRBi12;
376 case ARM::t2STRHi8: return ARM::t2STRHi12;
377 case ARM::t2PLDi8: return ARM::t2PLDi12;
379 case ARM::t2LDRi12:
380 case ARM::t2LDRHi12:
381 case ARM::t2LDRBi12:
382 case ARM::t2LDRSHi12:
383 case ARM::t2LDRSBi12:
384 case ARM::t2STRi12:
385 case ARM::t2STRBi12:
386 case ARM::t2STRHi12:
387 case ARM::t2PLDi12:
401 case ARM::t2LDRs: return ARM::t2LDRi12;
402 case ARM::t2LDRHs: return ARM::t2LDRHi12;
403 case ARM::t2LDRBs: return ARM::t2LDRBi12;
404 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
405 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
406 case ARM::t2STRs: return ARM::t2STRi12;
407 case ARM::t2STRBs: return ARM::t2STRBi12;
408 case ARM::t2STRHs: return ARM::t2STRHi12;
409 case ARM::t2PLDs: return ARM::t2PLDi12;
411 case ARM::t2LDRi12:
412 case ARM::t2LDRHi12:
413 case ARM::t2LDRBi12:
414 case ARM::t2LDRSHi12:
415 case ARM::t2LDRSBi12:
416 case ARM::t2STRi12:
417 case ARM::t2STRBi12:
418 case ARM::t2STRHi12:
419 case ARM::t2PLDi12:
420 case ARM::t2LDRi8:
421 case ARM::t2LDRHi8:
422 case ARM::t2LDRBi8:
423 case ARM::t2LDRSHi8:
424 case ARM::t2LDRSBi8:
425 case ARM::t2STRi8:
426 case ARM::t2STRBi8:
427 case ARM::t2STRHi8:
428 case ARM::t2PLDi8:
447 if (Opcode == ARM::INLINEASM)
450 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
456 MI.setDesc(TII.get(ARM::tMOVr));
466 bool HasCCOut = Opcode != ARM::t2ADDri12;
471 MI.setDesc(TII.get(ARM::t2SUBri));
473 MI.setDesc(TII.get(ARM::t2ADDri));
489 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
628 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)