Lines Matching refs:ARM
11 #include "ARM.h"
62 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
63 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
64 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
65 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
66 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
67 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
68 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
69 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
70 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
72 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
73 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
74 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
75 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
76 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
78 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
79 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
80 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
81 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
82 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
83 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
84 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
86 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
87 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
88 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
89 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
91 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
92 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
94 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
95 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
96 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
97 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
98 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
99 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
100 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
101 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
102 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
103 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
104 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
105 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
109 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
110 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
111 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
124 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
125 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
126 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
128 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
129 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
215 if (*Regs == ARM::CPSR)
223 case ARM::FMSTAT:
224 case ARM::tMUL:
264 if (Reg == 0 || Reg == ARM::CPSR)
284 if (Use->getOpcode() == ARM::t2MOVi ||
285 Use->getOpcode() == ARM::t2MOVi16)
337 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
338 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
339 Opc == ARM::t2LDMDB_UPD);
340 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
347 if (Reg == 0 || Reg == ARM::CPSR)
349 if (isPCOk && Reg == ARM::PC)
351 if (isLROk && Reg == ARM::LR)
353 if (Reg == ARM::SP) {
356 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
384 case ARM::t2LDRi12:
385 case ARM::t2STRi12:
386 if (MI->getOperand(1).getReg() == ARM::SP) {
396 case ARM::t2LDRBi12:
397 case ARM::t2STRBi12:
401 case ARM::t2LDRHi12:
402 case ARM::t2STRHi12:
407 case ARM::t2LDRs:
408 case ARM::t2LDRBs:
409 case ARM::t2LDRHs:
410 case ARM::t2LDRSBs:
411 case ARM::t2LDRSHs:
412 case ARM::t2STRs:
413 case ARM::t2STRBs:
414 case ARM::t2STRHs:
418 case ARM::t2LDMIA:
419 case ARM::t2LDMDB: {
421 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
441 case ARM::t2LDMIA_RET: {
443 if (BaseReg != ARM::SP)
450 case ARM::t2LDMIA_UPD:
451 case ARM::t2LDMDB_UPD:
452 case ARM::t2STMIA_UPD:
453 case ARM::t2STMDB_UPD: {
457 if (BaseReg == ARM::SP &&
458 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
459 Entry.WideOpc == ARM::t2STMDB_UPD)) {
463 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
464 Entry.WideOpc != ARM::t2STMIA_UPD)) {
532 if (Opc == ARM::t2ADDri) {
535 if (MI->getOperand(1).getReg() != ARM::SP) {
553 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
557 TII->get(ARM::tADDrSPi))
581 case ARM::t2ADDSri:
582 case ARM::t2ADDSrr: {
587 case ARM::t2ADDSri: {
592 case ARM::t2ADDSrr:
598 case ARM::t2RSBri:
599 case ARM::t2RSBSri:
600 case ARM::t2SXTB:
601 case ARM::t2SXTH:
602 case ARM::t2UXTB:
603 case ARM::t2UXTH:
607 case ARM::t2MOVi16:
613 case ARM::t2CMPrr: {
620 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
646 if (MI->getOpcode() == ARM::t2MUL) {
703 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
771 if (!Reg || Reg == ARM::CPSR)
799 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
828 if ((MCID.getOpcode() == ARM::t2RSBSri ||
829 MCID.getOpcode() == ARM::t2RSBri ||
830 MCID.getOpcode() == ARM::t2SXTB ||
831 MCID.getOpcode() == ARM::t2SXTH ||
832 MCID.getOpcode() == ARM::t2UXTB ||
833 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
840 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
865 if (MO.getReg() != ARM::CPSR)
881 if (MO.getReg() != ARM::CPSR)
922 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
978 if (BundleMI->killsRegister(ARM::CPSR))
980 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);