/haiku/src/add-ons/kernel/drivers/network/ether/sis900/dev/sis/ |
H A D | if_sis.c | 467 sis_miibus_readreg(device_t dev, int phy, int reg) argument 474 if (phy != 0) 500 if (phy != 0) 504 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 525 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy, 530 sis_miibus_writereg(device_t dev, int phy, int reg, int data) argument 537 if (phy != 0) 552 if (phy != 0) 555 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 568 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, re [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/dec21xxx/dev/dc/ |
H A D | if_dc.c | 662 dc_miibus_readreg(device_t dev, int phy, int reg) argument 670 if (phy == (MII_NPHY - 1)) { 695 (phy << 23) | (reg << 18)); 709 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 720 device_printf(dev, "phy read timed out\n"); 748 device_printf(dev, "phy_read: bad phy register %x\n", 763 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 771 dc_miibus_writereg(device_t dev, int phy, int reg, int data) argument 780 (phy << 23) | (reg << 10) | data); 790 ((phy << DC_ULI_PHY_ADDR_SHIF 2027 int error, mac_offset, n, phy, rid, tmp; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/ |
H A D | if_nfe.c | 935 uint32_t link, misc, phy, seed; local 940 phy = NFE_READ(sc, NFE_PHY_IFACE); 941 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 950 phy |= NFE_PHY_HDX; /* half-duplex */ 958 phy |= NFE_PHY_1000T; 963 phy |= NFE_PHY_100TX; 971 if ((phy & 0x10000000) != 0) { 982 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 1026 nfe_miibus_readreg(device_t dev, int phy, int reg) argument 1039 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIF 1067 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/3com/dev/xl/ |
H A D | if_xl.c | 417 xl_miibus_readreg(device_t dev, int phy, int reg) argument 426 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 430 xl_miibus_writereg(device_t dev, int phy, int reg, int data) argument 439 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 1075 int error = 0, phy, rid, res, unit; local 1406 phy = MII_PHY_ANY; 1408 phy = 24; 1410 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
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/haiku/src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/ |
H A D | if_vr.c | 244 vr_miibus_readreg(device_t dev, int phy, int reg) argument 261 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 267 vr_miibus_writereg(device_t dev, int phy, int reg, int data) argument 285 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 601 int i, phy, pmc; local 771 phy = 1; 773 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 775 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_AN [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/ |
H A D | rt2860reg.h | 820 uint16_t phy; member in struct:rt2860_txwi 890 uint16_t phy; member in struct:rt2860_rxwi 976 enum ieee80211_phytype phy; member in struct:rt2860_rate
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/haiku/src/add-ons/kernel/busses/virtio/virtio_pci/ |
H A D | virtio_pci.cpp | 415 setup_queue(void* cookie, uint16 queue, phys_addr_t phy, phys_addr_t phyAvail, argument 430 *queueDesc = phy; 447 (uint32)phy >> VIRTIO_PCI_QUEUE_ADDR_SHIFT);
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/haiku/src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/ |
H A D | if_bwi.c | 361 struct bwi_phy *phy; local 442 phy = &mac->mac_phy; 459 if (phy->phy_mode == IEEE80211_MODE_11B || 460 phy->phy_mode == IEEE80211_MODE_11G) { 461 if (phy->phy_mode == IEEE80211_MODE_11B) { 476 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 481 panic("unknown phymode %d\n", phy->phy_mode); 1693 struct bwi_phy *phy; local 1701 phy = &mac->mac_phy; 1704 switch (phy [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/usb/wlan/ |
H A D | if_run.c | 512 enum ieee80211_phytype phy; member in struct:rt2860_rate 2960 uint16_t phy; local 2972 phy = le16toh(rxwi->phy); 2973 switch (phy & RT2860_PHY_MODE) { 2975 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2981 if (phy & RT2860_PHY_SHPRE) 2985 switch (phy & RT2860_PHY_MCS) { 3250 if (le16toh(txwi->phy) & RT2860_PHY_SHPRE) 3394 if (rt2860_rates[ridx].phy [all...] |
H A D | if_runreg.h | 779 uint16_t phy; member in struct:rt2860_txwi 849 uint16_t phy; member in struct:rt2860_rxwi
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/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/ |
H A D | if_re.c | 448 re_gmii_readreg(device_t dev, int phy, int reg) argument 486 re_gmii_writereg(device_t dev, int phy, int reg, int data) argument 518 re_miibus_readreg(device_t dev, int phy, int reg) argument 527 rval = re_gmii_readreg(dev, phy, reg); 560 device_printf(sc->rl_dev, "bad phy register\n"); 572 re_miibus_writereg(device_t dev, int phy, int reg, int data) argument 581 rval = re_gmii_writereg(dev, phy, reg, data); 610 device_printf(sc->rl_dev, "bad phy register\n"); 1222 phy, reg, rid; local 1666 phy [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/rdc/dev/vte/ |
H A D | if_vte.c | 173 vte_miibus_readreg(device_t dev, int phy, int reg) argument 181 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 189 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg); 197 vte_miibus_writereg(device_t dev, int phy, int reg, int val) argument 206 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 214 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg);
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/haiku/src/add-ons/kernel/drivers/network/ether/wb840/ |
H A D | wb840.h | 367 uint16 phy; member in struct:wb_device
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/haiku/src/add-ons/kernel/drivers/network/ether/sis19x/dev/sge/ |
H A D | if_sge.c | 334 sge_miibus_readreg(device_t dev, int phy, int reg) argument 341 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) | 358 sge_miibus_writereg(device_t dev, int phy, int reg, int data) argument 365 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
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/haiku/src/add-ons/kernel/drivers/network/ether/intel22x/dev/igc/ |
H A D | igc_hw.h | 523 struct igc_phy_info phy; member in struct:igc_hw
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/haiku/src/add-ons/kernel/drivers/network/ether/atheros813x/dev/alc/ |
H A D | if_alc.c | 273 alc_miibus_readreg(device_t dev, int phy, int reg) argument 280 v = alc_mii_readreg_816x(sc, phy, reg); 282 v = alc_mii_readreg_813x(sc, phy, reg); 287 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) argument 312 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 320 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) argument 339 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 347 alc_miibus_writereg(device_t dev, int phy, int reg, int val) argument 354 v = alc_mii_writereg_816x(sc, phy, reg, val); 356 v = alc_mii_writereg_813x(sc, phy, re 361 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) argument 383 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) argument [all...] |
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi4965/dev/iwn/ |
H A D | if_iwn.c | 2861 * to map the ridx -> phy table entry 5869 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; local 5875 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5876 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5880 rssi = MAX(rssi, phy->rssi[0]); 5882 rssi = MAX(rssi, phy->rssi[2]); 5884 rssi = MAX(rssi, phy->rssi[4]); 5888 mask, phy->rssi[0], phy->rssi[2], phy 5896 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; local [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/attansic_l2/dev/ae/ |
H A D | if_ae.c | 114 static int ae_miibus_readreg(device_t dev, int phy, int reg); 115 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 808 ae_miibus_readreg(device_t dev, int phy, int reg) argument 836 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 843 ae_miibus_writereg(device_t dev, int phy, int reg, int val) argument 872 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ |
H A D | ah.c | 429 * using the specified rate, phy, and short preamble setting. 451 switch (rates->info[rateix].phy) { 508 "%s: unknown phy %u (rate ix %u)\n", 509 __func__, rates->info[rateix].phy, rateix);
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/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/ |
H A D | if_msk.c | 402 msk_miibus_readreg(device_t dev, int phy, int reg) argument 408 return (msk_phy_readreg(sc_if, phy, reg)); 412 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) argument 420 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 432 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 440 msk_miibus_writereg(device_t dev, int phy, int reg, int val) argument 446 return (msk_phy_writereg(sc_if, phy, reg, val)); 450 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) argument 459 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 467 if_printf(sc_if->msk_ifp, "phy writ [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/jmicron2x0/dev/jme/ |
H A D | if_jme.c | 217 jme_miibus_readreg(device_t dev, int phy, int reg) argument 226 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 230 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 238 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 249 jme_miibus_writereg(device_t dev, int phy, int reg, int val) argument 257 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 262 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 270 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 1521 * may be better handled in suspend method in phy driver.
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro100/dev/fxp/ |
H A D | if_fxp.c | 266 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 267 static int fxp_miibus_writereg(device_t dev, int phy, int reg, 2775 fxp_miibus_readreg(device_t dev, int phy, int reg) argument 2782 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2795 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) argument 2801 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
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/haiku/src/add-ons/kernel/drivers/network/ether/broadcom570x/dev/bce/ |
H A D | if_bcereg.h | 434 "%s(): phy = %d, reg = 0x%04X (BMCR ), val = 0x%b\n", \ 435 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 438 "%s(): phy = %d, reg = 0x%04X (BMSR ), val = 0x%b\n", \ 439 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 442 "%s(): phy = %d, reg = 0x%04X (ANAR ), val = 0x%b\n", \ 443 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 446 "%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n", \ 447 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 450 "%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n", \ 451 __FUNCTION__, phy, (u1 [all...] |
/haiku/src/add-ons/kernel/drivers/network/ether/broadcom440x/dev/bfe/ |
H A D | if_bfe.c | 629 bfe_miibus_readreg(device_t dev, int phy, int reg) argument 641 bfe_miibus_writereg(device_t dev, int phy, int reg, int val) argument 957 * We want the phy registers to be accessible even when 959 * and whether internal or external phy here. 962 /* 4402 has 62.5Mhz SB clock and internal phy */
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/ |
H A D | e1000_hw.h | 1030 struct e1000_phy_info phy; member in struct:e1000_hw
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