1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: releng/12.0/sys/dev/ae/if_ae.c 339735 2018-10-25 17:00:39Z brooks $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/mutex.h> 44#include <sys/rman.h> 45#include <sys/module.h> 46#include <sys/queue.h> 47#include <sys/socket.h> 48#include <sys/sockio.h> 49#include <sys/sysctl.h> 50#include <sys/taskqueue.h> 51 52#include <net/bpf.h> 53#include <net/if.h> 54#include <net/if_var.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60#include <net/if_vlan_var.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/ip.h> 65#include <netinet/tcp.h> 66 67#include <dev/mii/mii.h> 68#include <dev/mii/miivar.h> 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <machine/bus.h> 73 74#include "miibus_if.h" 75 76#include "if_aereg.h" 77#include "if_aevar.h" 78 79/* 80 * Devices supported by this driver. 81 */ 82static struct ae_dev { 83 uint16_t vendorid; 84 uint16_t deviceid; 85 const char *name; 86} ae_devs[] = { 87 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 88 "Attansic Technology Corp, L2 FastEthernet" }, 89}; 90#define AE_DEVS_COUNT nitems(ae_devs) 91 92static struct resource_spec ae_res_spec_mem[] = { 93 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 94 { -1, 0, 0 } 95}; 96static struct resource_spec ae_res_spec_irq[] = { 97 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 98 { -1, 0, 0 } 99}; 100static struct resource_spec ae_res_spec_msi[] = { 101 { SYS_RES_IRQ, 1, RF_ACTIVE }, 102 { -1, 0, 0 } 103}; 104 105static int ae_probe(device_t dev); 106static int ae_attach(device_t dev); 107static void ae_pcie_init(ae_softc_t *sc); 108static void ae_phy_reset(ae_softc_t *sc); 109static void ae_phy_init(ae_softc_t *sc); 110static int ae_reset(ae_softc_t *sc); 111static void ae_init(void *arg); 112static int ae_init_locked(ae_softc_t *sc); 113static int ae_detach(device_t dev); 114static int ae_miibus_readreg(device_t dev, int phy, int reg); 115static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 116static void ae_miibus_statchg(device_t dev); 117static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 118static int ae_mediachange(struct ifnet *ifp); 119static void ae_retrieve_address(ae_softc_t *sc); 120static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 121 int error); 122static int ae_alloc_rings(ae_softc_t *sc); 123static void ae_dma_free(ae_softc_t *sc); 124static int ae_shutdown(device_t dev); 125static int ae_suspend(device_t dev); 126static void ae_powersave_disable(ae_softc_t *sc); 127static void ae_powersave_enable(ae_softc_t *sc); 128static int ae_resume(device_t dev); 129static unsigned int ae_tx_avail_size(ae_softc_t *sc); 130static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 131static void ae_start(struct ifnet *ifp); 132static void ae_start_locked(struct ifnet *ifp); 133static void ae_link_task(void *arg, int pending); 134static void ae_stop_rxmac(ae_softc_t *sc); 135static void ae_stop_txmac(ae_softc_t *sc); 136static void ae_mac_config(ae_softc_t *sc); 137static int ae_intr(void *arg); 138static void ae_int_task(void *arg, int pending); 139static void ae_tx_intr(ae_softc_t *sc); 140static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 141static void ae_rx_intr(ae_softc_t *sc); 142static void ae_watchdog(ae_softc_t *sc); 143static void ae_tick(void *arg); 144static void ae_rxfilter(ae_softc_t *sc); 145static void ae_rxvlan(ae_softc_t *sc); 146static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 147static void ae_stop(ae_softc_t *sc); 148static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 149static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 150static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 151static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 152static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 153static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 154static void ae_init_tunables(ae_softc_t *sc); 155 156static device_method_t ae_methods[] = { 157 /* Device interface. */ 158 DEVMETHOD(device_probe, ae_probe), 159 DEVMETHOD(device_attach, ae_attach), 160 DEVMETHOD(device_detach, ae_detach), 161 DEVMETHOD(device_shutdown, ae_shutdown), 162 DEVMETHOD(device_suspend, ae_suspend), 163 DEVMETHOD(device_resume, ae_resume), 164 165 /* MII interface. */ 166 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 169 170 { NULL, NULL } 171}; 172static driver_t ae_driver = { 173 "ae", 174 ae_methods, 175 sizeof(ae_softc_t) 176}; 177static devclass_t ae_devclass; 178 179DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 180MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 181 nitems(ae_devs)); 182DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 183MODULE_DEPEND(ae, pci, 1, 1, 1); 184MODULE_DEPEND(ae, ether, 1, 1, 1); 185MODULE_DEPEND(ae, miibus, 1, 1, 1); 186 187/* 188 * Tunables. 189 */ 190static int msi_disable = 0; 191TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 192 193#define AE_READ_4(sc, reg) \ 194 bus_read_4((sc)->mem[0], (reg)) 195#define AE_READ_2(sc, reg) \ 196 bus_read_2((sc)->mem[0], (reg)) 197#define AE_READ_1(sc, reg) \ 198 bus_read_1((sc)->mem[0], (reg)) 199#define AE_WRITE_4(sc, reg, val) \ 200 bus_write_4((sc)->mem[0], (reg), (val)) 201#define AE_WRITE_2(sc, reg, val) \ 202 bus_write_2((sc)->mem[0], (reg), (val)) 203#define AE_WRITE_1(sc, reg, val) \ 204 bus_write_1((sc)->mem[0], (reg), (val)) 205#define AE_PHY_READ(sc, reg) \ 206 ae_miibus_readreg(sc->dev, 0, reg) 207#define AE_PHY_WRITE(sc, reg, val) \ 208 ae_miibus_writereg(sc->dev, 0, reg, val) 209#define AE_CHECK_EADDR_VALID(eaddr) \ 210 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 211 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 212#define AE_RXD_VLAN(vtag) \ 213 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 214#define AE_TXD_VLAN(vtag) \ 215 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 216 217static int 218ae_probe(device_t dev) 219{ 220 uint16_t deviceid, vendorid; 221 int i; 222 223 vendorid = pci_get_vendor(dev); 224 deviceid = pci_get_device(dev); 225 226 /* 227 * Search through the list of supported devs for matching one. 228 */ 229 for (i = 0; i < AE_DEVS_COUNT; i++) { 230 if (vendorid == ae_devs[i].vendorid && 231 deviceid == ae_devs[i].deviceid) { 232 device_set_desc(dev, ae_devs[i].name); 233 return (BUS_PROBE_DEFAULT); 234 } 235 } 236 return (ENXIO); 237} 238 239static int 240ae_attach(device_t dev) 241{ 242 ae_softc_t *sc; 243 struct ifnet *ifp; 244 uint8_t chiprev; 245 uint32_t pcirev; 246 int nmsi, pmc; 247 int error; 248 249 sc = device_get_softc(dev); /* Automatically allocated and zeroed 250 on attach. */ 251 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 252 sc->dev = dev; 253 254 /* 255 * Initialize mutexes and tasks. 256 */ 257 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 258 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 259 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 260 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 261 262 pci_enable_busmaster(dev); /* Enable bus mastering. */ 263 264 sc->spec_mem = ae_res_spec_mem; 265 266 /* 267 * Allocate memory-mapped registers. 268 */ 269 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 270 if (error != 0) { 271 device_printf(dev, "could not allocate memory resources.\n"); 272 sc->spec_mem = NULL; 273 goto fail; 274 } 275 276 /* 277 * Retrieve PCI and chip revisions. 278 */ 279 pcirev = pci_get_revid(dev); 280 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 281 AE_MASTER_REVNUM_MASK; 282 if (bootverbose) { 283 device_printf(dev, "pci device revision: %#04x\n", pcirev); 284 device_printf(dev, "chip id: %#02x\n", chiprev); 285 } 286 nmsi = pci_msi_count(dev); 287 if (bootverbose) 288 device_printf(dev, "MSI count: %d.\n", nmsi); 289 290 /* 291 * Allocate interrupt resources. 292 */ 293 if (msi_disable == 0 && nmsi == 1) { 294 error = pci_alloc_msi(dev, &nmsi); 295 if (error == 0) { 296 device_printf(dev, "Using MSI messages.\n"); 297 sc->spec_irq = ae_res_spec_msi; 298 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 299 if (error != 0) { 300 device_printf(dev, "MSI allocation failed.\n"); 301 sc->spec_irq = NULL; 302 pci_release_msi(dev); 303 } else { 304 sc->flags |= AE_FLAG_MSI; 305 } 306 } 307 } 308 if (sc->spec_irq == NULL) { 309 sc->spec_irq = ae_res_spec_irq; 310 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 311 if (error != 0) { 312 device_printf(dev, "could not allocate IRQ resources.\n"); 313 sc->spec_irq = NULL; 314 goto fail; 315 } 316 } 317 318 ae_init_tunables(sc); 319 320 ae_phy_reset(sc); /* Reset PHY. */ 321 error = ae_reset(sc); /* Reset the controller itself. */ 322 if (error != 0) 323 goto fail; 324 325 ae_pcie_init(sc); 326 327 ae_retrieve_address(sc); /* Load MAC address. */ 328 329 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 330 if (error != 0) 331 goto fail; 332 333 ifp = sc->ifp = if_alloc(IFT_ETHER); 334 if (ifp == NULL) { 335 device_printf(dev, "could not allocate ifnet structure.\n"); 336 error = ENXIO; 337 goto fail; 338 } 339 340 ifp->if_softc = sc; 341 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 343 ifp->if_ioctl = ae_ioctl; 344 ifp->if_start = ae_start; 345 ifp->if_init = ae_init; 346 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 347 ifp->if_hwassist = 0; 348 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 349 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 350 IFQ_SET_READY(&ifp->if_snd); 351 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 352 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 353 sc->flags |= AE_FLAG_PMG; 354 } 355 ifp->if_capenable = ifp->if_capabilities; 356 357 /* 358 * Configure and attach MII bus. 359 */ 360 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 361 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 362 MII_OFFSET_ANY, 0); 363 if (error != 0) { 364 device_printf(dev, "attaching PHYs failed\n"); 365 goto fail; 366 } 367 368 ether_ifattach(ifp, sc->eaddr); 369 /* Tell the upper layer(s) we support long frames. */ 370 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 371 372 /* 373 * Create and run all helper tasks. 374 */ 375 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 376 taskqueue_thread_enqueue, &sc->tq); 377 if (sc->tq == NULL) { 378 device_printf(dev, "could not create taskqueue.\n"); 379 ether_ifdetach(ifp); 380 error = ENXIO; 381 goto fail; 382 } 383 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 384 device_get_nameunit(sc->dev)); 385 386 /* 387 * Configure interrupt handlers. 388 */ 389 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 390 ae_intr, NULL, sc, &sc->intrhand); 391 if (error != 0) { 392 device_printf(dev, "could not set up interrupt handler.\n"); 393 taskqueue_free(sc->tq); 394 sc->tq = NULL; 395 ether_ifdetach(ifp); 396 goto fail; 397 } 398 399fail: 400 if (error != 0) 401 ae_detach(dev); 402 403 return (error); 404} 405 406#define AE_SYSCTL(stx, parent, name, desc, ptr) \ 407 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 408 409static void 410ae_init_tunables(ae_softc_t *sc) 411{ 412 struct sysctl_ctx_list *ctx; 413 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 414 struct ae_stats *ae_stats; 415 416 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 417 ae_stats = &sc->stats; 418 419 ctx = device_get_sysctl_ctx(sc->dev); 420 root = device_get_sysctl_tree(sc->dev); 421 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 422 CTLFLAG_RD, NULL, "ae statistics"); 423 424 /* 425 * Receiver statistcics. 426 */ 427 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 428 CTLFLAG_RD, NULL, "Rx MAC statistics"); 429 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 430 "broadcast frames", &ae_stats->rx_bcast); 431 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 432 "multicast frames", &ae_stats->rx_mcast); 433 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 434 "PAUSE frames", &ae_stats->rx_pause); 435 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 436 "control frames", &ae_stats->rx_ctrl); 437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 438 "frames with CRC errors", &ae_stats->rx_crcerr); 439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 440 "frames with invalid opcode", &ae_stats->rx_codeerr); 441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 442 "runt frames", &ae_stats->rx_runt); 443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 444 "fragmented frames", &ae_stats->rx_frag); 445 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 446 "frames with alignment errors", &ae_stats->rx_align); 447 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 448 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 449 450 /* 451 * Receiver statistcics. 452 */ 453 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 454 CTLFLAG_RD, NULL, "Tx MAC statistics"); 455 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 456 "broadcast frames", &ae_stats->tx_bcast); 457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 458 "multicast frames", &ae_stats->tx_mcast); 459 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 460 "PAUSE frames", &ae_stats->tx_pause); 461 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 462 "control frames", &ae_stats->tx_ctrl); 463 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 464 "deferrals occuried", &ae_stats->tx_defer); 465 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 466 "excessive deferrals occuried", &ae_stats->tx_excdefer); 467 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 468 "single collisions occuried", &ae_stats->tx_singlecol); 469 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 470 "multiple collisions occuried", &ae_stats->tx_multicol); 471 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 472 "late collisions occuried", &ae_stats->tx_latecol); 473 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 474 "transmit aborts due collisions", &ae_stats->tx_abortcol); 475 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 476 "Tx FIFO underruns", &ae_stats->tx_underrun); 477} 478 479static void 480ae_pcie_init(ae_softc_t *sc) 481{ 482 483 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 484 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 485} 486 487static void 488ae_phy_reset(ae_softc_t *sc) 489{ 490 491 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 492 DELAY(1000); /* XXX: pause(9) ? */ 493} 494 495static int 496ae_reset(ae_softc_t *sc) 497{ 498 int i; 499 500 /* 501 * Issue a soft reset. 502 */ 503 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 504 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 505 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 506 507 /* 508 * Wait for reset to complete. 509 */ 510 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 511 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 512 break; 513 DELAY(10); 514 } 515 if (i == AE_RESET_TIMEOUT) { 516 device_printf(sc->dev, "reset timeout.\n"); 517 return (ENXIO); 518 } 519 520 /* 521 * Wait for everything to enter idle state. 522 */ 523 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 524 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 525 break; 526 DELAY(100); 527 } 528 if (i == AE_IDLE_TIMEOUT) { 529 device_printf(sc->dev, "could not enter idle state.\n"); 530 return (ENXIO); 531 } 532 return (0); 533} 534 535static void 536ae_init(void *arg) 537{ 538 ae_softc_t *sc; 539 540 sc = (ae_softc_t *)arg; 541 AE_LOCK(sc); 542 ae_init_locked(sc); 543 AE_UNLOCK(sc); 544} 545 546static void 547ae_phy_init(ae_softc_t *sc) 548{ 549 550 /* 551 * Enable link status change interrupt. 552 * XXX magic numbers. 553 */ 554#ifdef notyet 555 AE_PHY_WRITE(sc, 18, 0xc00); 556#endif 557} 558 559static int 560ae_init_locked(ae_softc_t *sc) 561{ 562 struct ifnet *ifp; 563 struct mii_data *mii; 564 uint8_t eaddr[ETHER_ADDR_LEN]; 565 uint32_t val; 566 bus_addr_t addr; 567 568 AE_LOCK_ASSERT(sc); 569 570 ifp = sc->ifp; 571 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 572 return (0); 573 mii = device_get_softc(sc->miibus); 574 575 ae_stop(sc); 576 ae_reset(sc); 577 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 578 ae_phy_init(sc); 579 ae_powersave_disable(sc); 580 581 /* 582 * Clear and disable interrupts. 583 */ 584 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 585 586 /* 587 * Set the MAC address. 588 */ 589 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 590 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 591 AE_WRITE_4(sc, AE_EADDR0_REG, val); 592 val = eaddr[0] << 8 | eaddr[1]; 593 AE_WRITE_4(sc, AE_EADDR1_REG, val); 594 595 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 596 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 597 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 598 /* 599 * Set ring buffers base addresses. 600 */ 601 addr = sc->dma_rxd_busaddr; 602 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 603 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 604 addr = sc->dma_txd_busaddr; 605 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 606 addr = sc->dma_txs_busaddr; 607 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 608 609 /* 610 * Configure ring buffers sizes. 611 */ 612 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 613 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 614 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 615 616 /* 617 * Configure interframe gap parameters. 618 */ 619 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 620 AE_IFG_TXIPG_MASK) | 621 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 622 AE_IFG_RXIPG_MASK) | 623 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 624 AE_IFG_IPGR1_MASK) | 625 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 626 AE_IFG_IPGR2_MASK); 627 AE_WRITE_4(sc, AE_IFG_REG, val); 628 629 /* 630 * Configure half-duplex operation. 631 */ 632 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 633 AE_HDPX_LCOL_MASK) | 634 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 635 AE_HDPX_RETRY_MASK) | 636 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 637 AE_HDPX_ABEBT_MASK) | 638 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 639 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 640 AE_WRITE_4(sc, AE_HDPX_REG, val); 641 642 /* 643 * Configure interrupt moderate timer. 644 */ 645 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 646 val = AE_READ_4(sc, AE_MASTER_REG); 647 val |= AE_MASTER_IMT_EN; 648 AE_WRITE_4(sc, AE_MASTER_REG, val); 649 650 /* 651 * Configure interrupt clearing timer. 652 */ 653 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 654 655 /* 656 * Configure MTU. 657 */ 658 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 659 ETHER_CRC_LEN; 660 AE_WRITE_2(sc, AE_MTU_REG, val); 661 662 /* 663 * Configure cut-through threshold. 664 */ 665 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 666 667 /* 668 * Configure flow control. 669 */ 670 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 671 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 672 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 673 (AE_RXD_COUNT_DEFAULT / 12)); 674 675 /* 676 * Init mailboxes. 677 */ 678 sc->txd_cur = sc->rxd_cur = 0; 679 sc->txs_ack = sc->txd_ack = 0; 680 sc->rxd_cur = 0; 681 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 682 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 683 684 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 685 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 686 687 /* 688 * Enable DMA. 689 */ 690 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 691 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 692 693 /* 694 * Check if everything is OK. 695 */ 696 val = AE_READ_4(sc, AE_ISR_REG); 697 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 698 device_printf(sc->dev, "Initialization failed.\n"); 699 return (ENXIO); 700 } 701 702 /* 703 * Clear interrupt status. 704 */ 705 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 706 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 707 708 /* 709 * Enable interrupts. 710 */ 711 val = AE_READ_4(sc, AE_MASTER_REG); 712 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 713 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 714 715 /* 716 * Disable WOL. 717 */ 718 AE_WRITE_4(sc, AE_WOL_REG, 0); 719 720 /* 721 * Configure MAC. 722 */ 723 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 724 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 725 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 726 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 727 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 728 AE_MAC_PREAMBLE_MASK); 729 AE_WRITE_4(sc, AE_MAC_REG, val); 730 731 /* 732 * Configure Rx MAC. 733 */ 734 ae_rxfilter(sc); 735 ae_rxvlan(sc); 736 737 /* 738 * Enable Tx/Rx. 739 */ 740 val = AE_READ_4(sc, AE_MAC_REG); 741 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 742 743 sc->flags &= ~AE_FLAG_LINK; 744 mii_mediachg(mii); /* Switch to the current media. */ 745 746 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 747 748 ifp->if_drv_flags |= IFF_DRV_RUNNING; 749 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 750 751#ifdef AE_DEBUG 752 device_printf(sc->dev, "Initialization complete.\n"); 753#endif 754 755 return (0); 756} 757 758static int 759ae_detach(device_t dev) 760{ 761 struct ae_softc *sc; 762 struct ifnet *ifp; 763 764 sc = device_get_softc(dev); 765 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 766 ifp = sc->ifp; 767 if (device_is_attached(dev)) { 768 AE_LOCK(sc); 769 sc->flags |= AE_FLAG_DETACH; 770 ae_stop(sc); 771 AE_UNLOCK(sc); 772 callout_drain(&sc->tick_ch); 773 taskqueue_drain(sc->tq, &sc->int_task); 774 taskqueue_drain(taskqueue_swi, &sc->link_task); 775 ether_ifdetach(ifp); 776 } 777 if (sc->tq != NULL) { 778 taskqueue_drain(sc->tq, &sc->int_task); 779 taskqueue_free(sc->tq); 780 sc->tq = NULL; 781 } 782 if (sc->miibus != NULL) { 783 device_delete_child(dev, sc->miibus); 784 sc->miibus = NULL; 785 } 786 bus_generic_detach(sc->dev); 787 ae_dma_free(sc); 788 if (sc->intrhand != NULL) { 789 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 790 sc->intrhand = NULL; 791 } 792 if (ifp != NULL) { 793 if_free(ifp); 794 sc->ifp = NULL; 795 } 796 if (sc->spec_irq != NULL) 797 bus_release_resources(dev, sc->spec_irq, sc->irq); 798 if (sc->spec_mem != NULL) 799 bus_release_resources(dev, sc->spec_mem, sc->mem); 800 if ((sc->flags & AE_FLAG_MSI) != 0) 801 pci_release_msi(dev); 802 mtx_destroy(&sc->mtx); 803 804 return (0); 805} 806 807static int 808ae_miibus_readreg(device_t dev, int phy, int reg) 809{ 810 ae_softc_t *sc; 811 uint32_t val; 812 int i; 813 814 sc = device_get_softc(dev); 815 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 816 817 /* 818 * Locking is done in upper layers. 819 */ 820 821 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 822 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 823 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 824 AE_WRITE_4(sc, AE_MDIO_REG, val); 825 826 /* 827 * Wait for operation to complete. 828 */ 829 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 830 DELAY(2); 831 val = AE_READ_4(sc, AE_MDIO_REG); 832 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 833 break; 834 } 835 if (i == AE_MDIO_TIMEOUT) { 836 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 837 return (0); 838 } 839 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 840} 841 842static int 843ae_miibus_writereg(device_t dev, int phy, int reg, int val) 844{ 845 ae_softc_t *sc; 846 uint32_t aereg; 847 int i; 848 849 sc = device_get_softc(dev); 850 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 851 852 /* 853 * Locking is done in upper layers. 854 */ 855 856 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 857 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 858 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 859 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 860 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 861 862 /* 863 * Wait for operation to complete. 864 */ 865 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 866 DELAY(2); 867 aereg = AE_READ_4(sc, AE_MDIO_REG); 868 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 869 break; 870 } 871 if (i == AE_MDIO_TIMEOUT) { 872 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 873 } 874 return (0); 875} 876 877static void 878ae_miibus_statchg(device_t dev) 879{ 880 ae_softc_t *sc; 881 882 sc = device_get_softc(dev); 883 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 884} 885 886static void 887ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 888{ 889 ae_softc_t *sc; 890 struct mii_data *mii; 891 892 sc = ifp->if_softc; 893 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 894 895 AE_LOCK(sc); 896 mii = device_get_softc(sc->miibus); 897 mii_pollstat(mii); 898 ifmr->ifm_status = mii->mii_media_status; 899 ifmr->ifm_active = mii->mii_media_active; 900 AE_UNLOCK(sc); 901} 902 903static int 904ae_mediachange(struct ifnet *ifp) 905{ 906 ae_softc_t *sc; 907 struct mii_data *mii; 908 struct mii_softc *mii_sc; 909 int error; 910 911 /* XXX: check IFF_UP ?? */ 912 sc = ifp->if_softc; 913 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 914 AE_LOCK(sc); 915 mii = device_get_softc(sc->miibus); 916 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 917 PHY_RESET(mii_sc); 918 error = mii_mediachg(mii); 919 AE_UNLOCK(sc); 920 921 return (error); 922} 923 924static int 925ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 926{ 927 int error; 928 uint32_t val; 929 930 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 931 932 /* 933 * Not sure why, but Linux does this. 934 */ 935 val = AE_READ_4(sc, AE_SPICTL_REG); 936 if ((val & AE_SPICTL_VPD_EN) != 0) { 937 val &= ~AE_SPICTL_VPD_EN; 938 AE_WRITE_4(sc, AE_SPICTL_REG, val); 939 } 940 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 941 return (error); 942} 943 944static int 945ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 946{ 947 uint32_t val; 948 int i; 949 950 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 951 952 /* 953 * VPD registers start at offset 0x100. Read them. 954 */ 955 val = 0x100 + reg * 4; 956 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 957 AE_VPD_CAP_ADDR_MASK); 958 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 959 DELAY(2000); 960 val = AE_READ_4(sc, AE_VPD_CAP_REG); 961 if ((val & AE_VPD_CAP_DONE) != 0) 962 break; 963 } 964 if (i == AE_VPD_TIMEOUT) { 965 device_printf(sc->dev, "timeout reading VPD register %d.\n", 966 reg); 967 return (ETIMEDOUT); 968 } 969 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 970 return (0); 971} 972 973static int 974ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 975{ 976 uint32_t word, reg, val; 977 int error; 978 int found; 979 int vpdc; 980 int i; 981 982 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 983 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 984 985 /* 986 * Check for EEPROM. 987 */ 988 error = ae_check_eeprom_present(sc, &vpdc); 989 if (error != 0) 990 return (error); 991 992 /* 993 * Read the VPD configuration space. 994 * Each register is prefixed with signature, 995 * so we can check if it is valid. 996 */ 997 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 998 error = ae_vpd_read_word(sc, i, &word); 999 if (error != 0) 1000 break; 1001 1002 /* 1003 * Check signature. 1004 */ 1005 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1006 break; 1007 reg = word >> AE_VPD_REG_SHIFT; 1008 i++; /* Move to the next word. */ 1009 1010 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1011 continue; 1012 1013 error = ae_vpd_read_word(sc, i, &val); 1014 if (error != 0) 1015 break; 1016 if (reg == AE_EADDR0_REG) 1017 eaddr[0] = val; 1018 else 1019 eaddr[1] = val; 1020 found++; 1021 } 1022 1023 if (found < 2) 1024 return (ENOENT); 1025 1026 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1027 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1028 if (bootverbose) 1029 device_printf(sc->dev, 1030 "VPD ethernet address registers are invalid.\n"); 1031 return (EINVAL); 1032 } 1033 return (0); 1034} 1035 1036static int 1037ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1038{ 1039 1040 /* 1041 * BIOS is supposed to set this. 1042 */ 1043 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1044 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1045 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1046 1047 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1048 if (bootverbose) 1049 device_printf(sc->dev, 1050 "Ethernet address registers are invalid.\n"); 1051 return (EINVAL); 1052 } 1053 return (0); 1054} 1055 1056static void 1057ae_retrieve_address(ae_softc_t *sc) 1058{ 1059 uint32_t eaddr[2] = {0, 0}; 1060 int error; 1061 1062 /* 1063 *Check for EEPROM. 1064 */ 1065 error = ae_get_vpd_eaddr(sc, eaddr); 1066 if (error != 0) 1067 error = ae_get_reg_eaddr(sc, eaddr); 1068 if (error != 0) { 1069 if (bootverbose) 1070 device_printf(sc->dev, 1071 "Generating random ethernet address.\n"); 1072 eaddr[0] = arc4random(); 1073 1074 /* 1075 * Set OUI to ASUSTek COMPUTER INC. 1076 */ 1077 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1078 sc->eaddr[1] = 0x1f; 1079 sc->eaddr[2] = 0xc6; 1080 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1081 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1082 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1083 } else { 1084 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1085 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1086 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1087 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1088 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1089 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1090 } 1091} 1092 1093static void 1094ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1095{ 1096 bus_addr_t *addr = arg; 1097 1098 if (error != 0) 1099 return; 1100 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1101 nsegs)); 1102 *addr = segs[0].ds_addr; 1103} 1104 1105static int 1106ae_alloc_rings(ae_softc_t *sc) 1107{ 1108 bus_addr_t busaddr; 1109 int error; 1110 1111 /* 1112 * Create parent DMA tag. 1113 */ 1114 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1115 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1116 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1117 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1118 &sc->dma_parent_tag); 1119 if (error != 0) { 1120 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1121 return (error); 1122 } 1123 1124 /* 1125 * Create DMA tag for TxD. 1126 */ 1127 error = bus_dma_tag_create(sc->dma_parent_tag, 1128 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1129 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1130 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1131 &sc->dma_txd_tag); 1132 if (error != 0) { 1133 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1134 return (error); 1135 } 1136 1137 /* 1138 * Create DMA tag for TxS. 1139 */ 1140 error = bus_dma_tag_create(sc->dma_parent_tag, 1141 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1142 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1143 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1144 &sc->dma_txs_tag); 1145 if (error != 0) { 1146 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1147 return (error); 1148 } 1149 1150 /* 1151 * Create DMA tag for RxD. 1152 */ 1153 error = bus_dma_tag_create(sc->dma_parent_tag, 1154 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1155 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1156 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1157 &sc->dma_rxd_tag); 1158 if (error != 0) { 1159 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1160 return (error); 1161 } 1162 1163 /* 1164 * Allocate TxD DMA memory. 1165 */ 1166 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1167 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1168 &sc->dma_txd_map); 1169 if (error != 0) { 1170 device_printf(sc->dev, 1171 "could not allocate DMA memory for TxD ring.\n"); 1172 return (error); 1173 } 1174 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1175 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1176 if (error != 0 || busaddr == 0) { 1177 device_printf(sc->dev, 1178 "could not load DMA map for TxD ring.\n"); 1179 return (error); 1180 } 1181 sc->dma_txd_busaddr = busaddr; 1182 1183 /* 1184 * Allocate TxS DMA memory. 1185 */ 1186 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1187 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1188 &sc->dma_txs_map); 1189 if (error != 0) { 1190 device_printf(sc->dev, 1191 "could not allocate DMA memory for TxS ring.\n"); 1192 return (error); 1193 } 1194 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1195 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1196 if (error != 0 || busaddr == 0) { 1197 device_printf(sc->dev, 1198 "could not load DMA map for TxS ring.\n"); 1199 return (error); 1200 } 1201 sc->dma_txs_busaddr = busaddr; 1202 1203 /* 1204 * Allocate RxD DMA memory. 1205 */ 1206 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1207 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1208 &sc->dma_rxd_map); 1209 if (error != 0) { 1210 device_printf(sc->dev, 1211 "could not allocate DMA memory for RxD ring.\n"); 1212 return (error); 1213 } 1214 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1215 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1216 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1217 if (error != 0 || busaddr == 0) { 1218 device_printf(sc->dev, 1219 "could not load DMA map for RxD ring.\n"); 1220 return (error); 1221 } 1222 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1223 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1224 1225 return (0); 1226} 1227 1228static void 1229ae_dma_free(ae_softc_t *sc) 1230{ 1231 1232 if (sc->dma_txd_tag != NULL) { 1233 if (sc->dma_txd_busaddr != 0) 1234 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1235 if (sc->txd_base != NULL) 1236 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1237 sc->dma_txd_map); 1238 bus_dma_tag_destroy(sc->dma_txd_tag); 1239 sc->dma_txd_tag = NULL; 1240 sc->txd_base = NULL; 1241 sc->dma_txd_busaddr = 0; 1242 } 1243 if (sc->dma_txs_tag != NULL) { 1244 if (sc->dma_txs_busaddr != 0) 1245 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1246 if (sc->txs_base != NULL) 1247 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1248 sc->dma_txs_map); 1249 bus_dma_tag_destroy(sc->dma_txs_tag); 1250 sc->dma_txs_tag = NULL; 1251 sc->txs_base = NULL; 1252 sc->dma_txs_busaddr = 0; 1253 } 1254 if (sc->dma_rxd_tag != NULL) { 1255 if (sc->dma_rxd_busaddr != 0) 1256 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1257 if (sc->rxd_base_dma != NULL) 1258 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1259 sc->dma_rxd_map); 1260 bus_dma_tag_destroy(sc->dma_rxd_tag); 1261 sc->dma_rxd_tag = NULL; 1262 sc->rxd_base_dma = NULL; 1263 sc->dma_rxd_busaddr = 0; 1264 } 1265 if (sc->dma_parent_tag != NULL) { 1266 bus_dma_tag_destroy(sc->dma_parent_tag); 1267 sc->dma_parent_tag = NULL; 1268 } 1269} 1270 1271static int 1272ae_shutdown(device_t dev) 1273{ 1274 ae_softc_t *sc; 1275 int error; 1276 1277 sc = device_get_softc(dev); 1278 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1279 1280 error = ae_suspend(dev); 1281 AE_LOCK(sc); 1282 ae_powersave_enable(sc); 1283 AE_UNLOCK(sc); 1284 return (error); 1285} 1286 1287static void 1288ae_powersave_disable(ae_softc_t *sc) 1289{ 1290 uint32_t val; 1291 1292 AE_LOCK_ASSERT(sc); 1293 1294 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1295 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1296 if (val & AE_PHY_DBG_POWERSAVE) { 1297 val &= ~AE_PHY_DBG_POWERSAVE; 1298 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1299 DELAY(1000); 1300 } 1301} 1302 1303static void 1304ae_powersave_enable(ae_softc_t *sc) 1305{ 1306 uint32_t val; 1307 1308 AE_LOCK_ASSERT(sc); 1309 1310 /* 1311 * XXX magic numbers. 1312 */ 1313 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1314 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1316 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1317 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1318 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1319 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1320} 1321 1322static void 1323ae_pm_init(ae_softc_t *sc) 1324{ 1325 struct ifnet *ifp; 1326 uint32_t val; 1327 uint16_t pmstat; 1328 struct mii_data *mii; 1329 int pmc; 1330 1331 AE_LOCK_ASSERT(sc); 1332 1333 ifp = sc->ifp; 1334 if ((sc->flags & AE_FLAG_PMG) == 0) { 1335 /* Disable WOL entirely. */ 1336 AE_WRITE_4(sc, AE_WOL_REG, 0); 1337 return; 1338 } 1339 1340 /* 1341 * Configure WOL if enabled. 1342 */ 1343 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1344 mii = device_get_softc(sc->miibus); 1345 mii_pollstat(mii); 1346 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1347 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1348 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1349 AE_WOL_MAGIC_PME); 1350 1351 /* 1352 * Configure MAC. 1353 */ 1354 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1355 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1356 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1357 AE_HALFBUF_MASK) | \ 1358 ((AE_MAC_PREAMBLE_DEFAULT << \ 1359 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1360 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1361 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1362 IFM_FDX) != 0) 1363 val |= AE_MAC_FULL_DUPLEX; 1364 AE_WRITE_4(sc, AE_MAC_REG, val); 1365 1366 } else { /* No link. */ 1367 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1368 AE_WOL_LNKCHG_PME); 1369 AE_WRITE_4(sc, AE_MAC_REG, 0); 1370 } 1371 } else { 1372 ae_powersave_enable(sc); 1373 } 1374 1375 /* 1376 * PCIE hacks. Magic numbers. 1377 */ 1378 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1379 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1380 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1381 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1382 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1383 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1384 1385 /* 1386 * Configure PME. 1387 */ 1388 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1389 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1390 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1391 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1392 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1393 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1394 } 1395} 1396 1397static int 1398ae_suspend(device_t dev) 1399{ 1400 ae_softc_t *sc; 1401 1402 sc = device_get_softc(dev); 1403 1404 AE_LOCK(sc); 1405 ae_stop(sc); 1406 ae_pm_init(sc); 1407 AE_UNLOCK(sc); 1408 1409 return (0); 1410} 1411 1412static int 1413ae_resume(device_t dev) 1414{ 1415 ae_softc_t *sc; 1416 1417 sc = device_get_softc(dev); 1418 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1419 1420 AE_LOCK(sc); 1421 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1422 if ((sc->ifp->if_flags & IFF_UP) != 0) 1423 ae_init_locked(sc); 1424 AE_UNLOCK(sc); 1425 1426 return (0); 1427} 1428 1429static unsigned int 1430ae_tx_avail_size(ae_softc_t *sc) 1431{ 1432 unsigned int avail; 1433 1434 if (sc->txd_cur >= sc->txd_ack) 1435 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1436 else 1437 avail = sc->txd_ack - sc->txd_cur; 1438 1439 return (avail); 1440} 1441 1442static int 1443ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1444{ 1445 struct mbuf *m0; 1446 ae_txd_t *hdr; 1447 unsigned int to_end; 1448 uint16_t len; 1449 1450 AE_LOCK_ASSERT(sc); 1451 1452 m0 = *m_head; 1453 len = m0->m_pkthdr.len; 1454 1455 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1456 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1457#ifdef AE_DEBUG 1458 if_printf(sc->ifp, "No free Tx available.\n"); 1459#endif 1460 return ENOBUFS; 1461 } 1462 1463 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1464 bzero(hdr, sizeof(*hdr)); 1465 /* Skip header size. */ 1466 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1467 /* Space available to the end of the ring */ 1468 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1469 if (to_end >= len) { 1470 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1471 } else { 1472 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1473 sc->txd_cur)); 1474 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1475 } 1476 1477 /* 1478 * Set TxD flags and parameters. 1479 */ 1480 if ((m0->m_flags & M_VLANTAG) != 0) { 1481 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1482 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1483 } else { 1484 hdr->len = htole16(len); 1485 } 1486 1487 /* 1488 * Set current TxD position and round up to a 4-byte boundary. 1489 */ 1490 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1491 if (sc->txd_cur == sc->txd_ack) 1492 sc->flags &= ~AE_FLAG_TXAVAIL; 1493#ifdef AE_DEBUG 1494 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1495#endif 1496 1497 /* 1498 * Update TxS position and check if there are empty TxS available. 1499 */ 1500 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1501 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1502 if (sc->txs_cur == sc->txs_ack) 1503 sc->flags &= ~AE_FLAG_TXAVAIL; 1504 1505 /* 1506 * Synchronize DMA memory. 1507 */ 1508 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1509 BUS_DMASYNC_PREWRITE); 1510 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1512 1513 return (0); 1514} 1515 1516static void 1517ae_start(struct ifnet *ifp) 1518{ 1519 ae_softc_t *sc; 1520 1521 sc = ifp->if_softc; 1522 AE_LOCK(sc); 1523 ae_start_locked(ifp); 1524 AE_UNLOCK(sc); 1525} 1526 1527static void 1528ae_start_locked(struct ifnet *ifp) 1529{ 1530 ae_softc_t *sc; 1531 unsigned int count; 1532 struct mbuf *m0; 1533 int error; 1534 1535 sc = ifp->if_softc; 1536 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1537 AE_LOCK_ASSERT(sc); 1538 1539#ifdef AE_DEBUG 1540 if_printf(ifp, "Start called.\n"); 1541#endif 1542 1543 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1544 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1545 return; 1546 1547 count = 0; 1548 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1549 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1550 if (m0 == NULL) 1551 break; /* Nothing to do. */ 1552 1553 error = ae_encap(sc, &m0); 1554 if (error != 0) { 1555 if (m0 != NULL) { 1556 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1557 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1558#ifdef AE_DEBUG 1559 if_printf(ifp, "Setting OACTIVE.\n"); 1560#endif 1561 } 1562 break; 1563 } 1564 count++; 1565 sc->tx_inproc++; 1566 1567 /* Bounce a copy of the frame to BPF. */ 1568 ETHER_BPF_MTAP(ifp, m0); 1569 1570 m_freem(m0); 1571 } 1572 1573 if (count > 0) { /* Something was dequeued. */ 1574 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1575 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1576#ifdef AE_DEBUG 1577 if_printf(ifp, "%d packets dequeued.\n", count); 1578 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1579#endif 1580 } 1581} 1582 1583static void 1584ae_link_task(void *arg, int pending) 1585{ 1586 ae_softc_t *sc; 1587 struct mii_data *mii; 1588 struct ifnet *ifp; 1589 uint32_t val; 1590 1591 sc = (ae_softc_t *)arg; 1592 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1593 AE_LOCK(sc); 1594 1595 ifp = sc->ifp; 1596 mii = device_get_softc(sc->miibus); 1597 if (mii == NULL || ifp == NULL || 1598 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1599 AE_UNLOCK(sc); /* XXX: could happen? */ 1600 return; 1601 } 1602 1603 sc->flags &= ~AE_FLAG_LINK; 1604 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1605 (IFM_AVALID | IFM_ACTIVE)) { 1606 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1607 case IFM_10_T: 1608 case IFM_100_TX: 1609 sc->flags |= AE_FLAG_LINK; 1610 break; 1611 default: 1612 break; 1613 } 1614 } 1615 1616 /* 1617 * Stop Rx/Tx MACs. 1618 */ 1619 ae_stop_rxmac(sc); 1620 ae_stop_txmac(sc); 1621 1622 if ((sc->flags & AE_FLAG_LINK) != 0) { 1623 ae_mac_config(sc); 1624 1625 /* 1626 * Restart DMA engines. 1627 */ 1628 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1629 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1630 1631 /* 1632 * Enable Rx and Tx MACs. 1633 */ 1634 val = AE_READ_4(sc, AE_MAC_REG); 1635 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1636 AE_WRITE_4(sc, AE_MAC_REG, val); 1637 } 1638 AE_UNLOCK(sc); 1639} 1640 1641static void 1642ae_stop_rxmac(ae_softc_t *sc) 1643{ 1644 uint32_t val; 1645 int i; 1646 1647 AE_LOCK_ASSERT(sc); 1648 1649 /* 1650 * Stop Rx MAC engine. 1651 */ 1652 val = AE_READ_4(sc, AE_MAC_REG); 1653 if ((val & AE_MAC_RX_EN) != 0) { 1654 val &= ~AE_MAC_RX_EN; 1655 AE_WRITE_4(sc, AE_MAC_REG, val); 1656 } 1657 1658 /* 1659 * Stop Rx DMA engine. 1660 */ 1661 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1662 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1663 1664 /* 1665 * Wait for IDLE state. 1666 */ 1667 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1668 val = AE_READ_4(sc, AE_IDLE_REG); 1669 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1670 break; 1671 DELAY(100); 1672 } 1673 if (i == AE_IDLE_TIMEOUT) 1674 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1675} 1676 1677static void 1678ae_stop_txmac(ae_softc_t *sc) 1679{ 1680 uint32_t val; 1681 int i; 1682 1683 AE_LOCK_ASSERT(sc); 1684 1685 /* 1686 * Stop Tx MAC engine. 1687 */ 1688 val = AE_READ_4(sc, AE_MAC_REG); 1689 if ((val & AE_MAC_TX_EN) != 0) { 1690 val &= ~AE_MAC_TX_EN; 1691 AE_WRITE_4(sc, AE_MAC_REG, val); 1692 } 1693 1694 /* 1695 * Stop Tx DMA engine. 1696 */ 1697 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1698 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1699 1700 /* 1701 * Wait for IDLE state. 1702 */ 1703 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1704 val = AE_READ_4(sc, AE_IDLE_REG); 1705 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1706 break; 1707 DELAY(100); 1708 } 1709 if (i == AE_IDLE_TIMEOUT) 1710 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1711} 1712 1713static void 1714ae_mac_config(ae_softc_t *sc) 1715{ 1716 struct mii_data *mii; 1717 uint32_t val; 1718 1719 AE_LOCK_ASSERT(sc); 1720 1721 mii = device_get_softc(sc->miibus); 1722 val = AE_READ_4(sc, AE_MAC_REG); 1723 val &= ~AE_MAC_FULL_DUPLEX; 1724 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1725 1726 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1727 val |= AE_MAC_FULL_DUPLEX; 1728 1729 AE_WRITE_4(sc, AE_MAC_REG, val); 1730} 1731 1732static int 1733ae_intr(void *arg) 1734{ 1735 ae_softc_t *sc; 1736 uint32_t val; 1737 1738 sc = (ae_softc_t *)arg; 1739 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1740 1741 val = AE_READ_4(sc, AE_ISR_REG); 1742 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1743 return (FILTER_STRAY); 1744 1745 /* Disable interrupts. */ 1746 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1747 1748 /* Schedule interrupt processing. */ 1749 taskqueue_enqueue(sc->tq, &sc->int_task); 1750 1751 return (FILTER_HANDLED); 1752} 1753 1754static void 1755ae_int_task(void *arg, int pending) 1756{ 1757 ae_softc_t *sc; 1758 struct ifnet *ifp; 1759 uint32_t val; 1760 1761 sc = (ae_softc_t *)arg; 1762 1763 AE_LOCK(sc); 1764 1765 ifp = sc->ifp; 1766 1767 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1768 if (val == 0) { 1769 AE_UNLOCK(sc); 1770 return; 1771 } 1772 1773 /* 1774 * Clear interrupts and disable them. 1775 */ 1776 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1777 1778#ifdef AE_DEBUG 1779 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1780#endif 1781 1782 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1783 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1784 AE_ISR_PHY_LINKDOWN)) != 0) { 1785 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1786 ae_init_locked(sc); 1787 AE_UNLOCK(sc); 1788 return; 1789 } 1790 if ((val & AE_ISR_TX_EVENT) != 0) 1791 ae_tx_intr(sc); 1792 if ((val & AE_ISR_RX_EVENT) != 0) 1793 ae_rx_intr(sc); 1794 /* 1795 * Re-enable interrupts. 1796 */ 1797 AE_WRITE_4(sc, AE_ISR_REG, 0); 1798 1799 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1800 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1801 ae_start_locked(ifp); 1802 } 1803 } 1804 1805 AE_UNLOCK(sc); 1806} 1807 1808static void 1809ae_tx_intr(ae_softc_t *sc) 1810{ 1811 struct ifnet *ifp; 1812 ae_txd_t *txd; 1813 ae_txs_t *txs; 1814 uint16_t flags; 1815 1816 AE_LOCK_ASSERT(sc); 1817 1818 ifp = sc->ifp; 1819 1820#ifdef AE_DEBUG 1821 if_printf(ifp, "Tx interrupt occuried.\n"); 1822#endif 1823 1824 /* 1825 * Syncronize DMA buffers. 1826 */ 1827 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1828 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1829 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1830 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1831 1832 for (;;) { 1833 txs = sc->txs_base + sc->txs_ack; 1834 flags = le16toh(txs->flags); 1835 if ((flags & AE_TXS_UPDATE) == 0) 1836 break; 1837 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1838 /* Update stats. */ 1839 ae_update_stats_tx(flags, &sc->stats); 1840 1841 /* 1842 * Update TxS position. 1843 */ 1844 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1845 sc->flags |= AE_FLAG_TXAVAIL; 1846 1847 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1848 if (txs->len != txd->len) 1849 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1850 le16toh(txs->len), le16toh(txd->len)); 1851 1852 /* 1853 * Move txd ack and align on 4-byte boundary. 1854 */ 1855 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1856 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1857 1858 if ((flags & AE_TXS_SUCCESS) != 0) 1859 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1860 else 1861 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1862 1863 sc->tx_inproc--; 1864 } 1865 1866 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1867 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1868 if (sc->tx_inproc < 0) { 1869 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1870 sc->tx_inproc = 0; 1871 } 1872 1873 if (sc->tx_inproc == 0) 1874 sc->wd_timer = 0; /* Unarm watchdog. */ 1875 1876 /* 1877 * Syncronize DMA buffers. 1878 */ 1879 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1881 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1883} 1884 1885static void 1886ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1887{ 1888 struct ifnet *ifp; 1889 struct mbuf *m; 1890 unsigned int size; 1891 uint16_t flags; 1892 1893 AE_LOCK_ASSERT(sc); 1894 1895 ifp = sc->ifp; 1896 flags = le16toh(rxd->flags); 1897 1898#ifdef AE_DEBUG 1899 if_printf(ifp, "Rx interrupt occuried.\n"); 1900#endif 1901 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1902 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1903 if_printf(ifp, "Runt frame received."); 1904 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1905 return; 1906 } 1907 1908 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1909 if (m == NULL) { 1910 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1911 return; 1912 } 1913 1914 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1915 (flags & AE_RXD_HAS_VLAN) != 0) { 1916 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1917 m->m_flags |= M_VLANTAG; 1918 } 1919 1920 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1921 /* 1922 * Pass it through. 1923 */ 1924 AE_UNLOCK(sc); 1925 (*ifp->if_input)(ifp, m); 1926 AE_LOCK(sc); 1927} 1928 1929static void 1930ae_rx_intr(ae_softc_t *sc) 1931{ 1932 ae_rxd_t *rxd; 1933 struct ifnet *ifp; 1934 uint16_t flags; 1935 int count; 1936 1937 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1938 1939 AE_LOCK_ASSERT(sc); 1940 1941 ifp = sc->ifp; 1942 1943 /* 1944 * Syncronize DMA buffers. 1945 */ 1946 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1948 1949 for (count = 0;; count++) { 1950 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1951 flags = le16toh(rxd->flags); 1952 if ((flags & AE_RXD_UPDATE) == 0) 1953 break; 1954 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1955 /* Update stats. */ 1956 ae_update_stats_rx(flags, &sc->stats); 1957 1958 /* 1959 * Update position index. 1960 */ 1961 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1962 1963 if ((flags & AE_RXD_SUCCESS) != 0) 1964 ae_rxeof(sc, rxd); 1965 else 1966 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1967 } 1968 1969 if (count > 0) { 1970 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1971 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1972 /* 1973 * Update Rx index. 1974 */ 1975 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1976 } 1977} 1978 1979static void 1980ae_watchdog(ae_softc_t *sc) 1981{ 1982 struct ifnet *ifp; 1983 1984 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1985 AE_LOCK_ASSERT(sc); 1986 ifp = sc->ifp; 1987 1988 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1989 return; /* Noting to do. */ 1990 1991 if ((sc->flags & AE_FLAG_LINK) == 0) 1992 if_printf(ifp, "watchdog timeout (missed link).\n"); 1993 else 1994 if_printf(ifp, "watchdog timeout - resetting.\n"); 1995 1996 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1997 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1998 ae_init_locked(sc); 1999 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2000 ae_start_locked(ifp); 2001} 2002 2003static void 2004ae_tick(void *arg) 2005{ 2006 ae_softc_t *sc; 2007 struct mii_data *mii; 2008 2009 sc = (ae_softc_t *)arg; 2010 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2011 AE_LOCK_ASSERT(sc); 2012 2013 mii = device_get_softc(sc->miibus); 2014 mii_tick(mii); 2015 ae_watchdog(sc); /* Watchdog check. */ 2016 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2017} 2018 2019static void 2020ae_rxvlan(ae_softc_t *sc) 2021{ 2022 struct ifnet *ifp; 2023 uint32_t val; 2024 2025 AE_LOCK_ASSERT(sc); 2026 ifp = sc->ifp; 2027 val = AE_READ_4(sc, AE_MAC_REG); 2028 val &= ~AE_MAC_RMVLAN_EN; 2029 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2030 val |= AE_MAC_RMVLAN_EN; 2031 AE_WRITE_4(sc, AE_MAC_REG, val); 2032} 2033 2034static void 2035ae_rxfilter(ae_softc_t *sc) 2036{ 2037 struct ifnet *ifp; 2038 struct ifmultiaddr *ifma; 2039 uint32_t crc; 2040 uint32_t mchash[2]; 2041 uint32_t rxcfg; 2042 2043 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2044 2045 AE_LOCK_ASSERT(sc); 2046 2047 ifp = sc->ifp; 2048 2049 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2050 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2051 2052 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2053 rxcfg |= AE_MAC_BCAST_EN; 2054 if ((ifp->if_flags & IFF_PROMISC) != 0) 2055 rxcfg |= AE_MAC_PROMISC_EN; 2056 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2057 rxcfg |= AE_MAC_MCAST_EN; 2058 2059 /* 2060 * Wipe old settings. 2061 */ 2062 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2063 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2064 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2065 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2066 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2067 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2068 return; 2069 } 2070 2071 /* 2072 * Load multicast tables. 2073 */ 2074 bzero(mchash, sizeof(mchash)); 2075 if_maddr_rlock(ifp); 2076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2077 if (ifma->ifma_addr->sa_family != AF_LINK) 2078 continue; 2079 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2080 ifma->ifma_addr), ETHER_ADDR_LEN); 2081 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2082 } 2083 if_maddr_runlock(ifp); 2084 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2085 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2086 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2087} 2088 2089static int 2090ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2091{ 2092 struct ae_softc *sc; 2093 struct ifreq *ifr; 2094 struct mii_data *mii; 2095 int error, mask; 2096 2097 sc = ifp->if_softc; 2098 ifr = (struct ifreq *)data; 2099 error = 0; 2100 2101 switch (cmd) { 2102 case SIOCSIFMTU: 2103 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2104 error = EINVAL; 2105 else if (ifp->if_mtu != ifr->ifr_mtu) { 2106 AE_LOCK(sc); 2107 ifp->if_mtu = ifr->ifr_mtu; 2108 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2109 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2110 ae_init_locked(sc); 2111 } 2112 AE_UNLOCK(sc); 2113 } 2114 break; 2115 case SIOCSIFFLAGS: 2116 AE_LOCK(sc); 2117 if ((ifp->if_flags & IFF_UP) != 0) { 2118 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2119 if (((ifp->if_flags ^ sc->if_flags) 2120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2121 ae_rxfilter(sc); 2122 } else { 2123 if ((sc->flags & AE_FLAG_DETACH) == 0) 2124 ae_init_locked(sc); 2125 } 2126 } else { 2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2128 ae_stop(sc); 2129 } 2130 sc->if_flags = ifp->if_flags; 2131 AE_UNLOCK(sc); 2132 break; 2133 case SIOCADDMULTI: 2134 case SIOCDELMULTI: 2135 AE_LOCK(sc); 2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2137 ae_rxfilter(sc); 2138 AE_UNLOCK(sc); 2139 break; 2140 case SIOCSIFMEDIA: 2141 case SIOCGIFMEDIA: 2142 mii = device_get_softc(sc->miibus); 2143 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2144 break; 2145 case SIOCSIFCAP: 2146 AE_LOCK(sc); 2147 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2148 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2149 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2150 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2151 ae_rxvlan(sc); 2152 } 2153 VLAN_CAPABILITIES(ifp); 2154 AE_UNLOCK(sc); 2155 break; 2156 default: 2157 error = ether_ioctl(ifp, cmd, data); 2158 break; 2159 } 2160 return (error); 2161} 2162 2163static void 2164ae_stop(ae_softc_t *sc) 2165{ 2166 struct ifnet *ifp; 2167 int i; 2168 2169 AE_LOCK_ASSERT(sc); 2170 2171 ifp = sc->ifp; 2172 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2173 sc->flags &= ~AE_FLAG_LINK; 2174 sc->wd_timer = 0; /* Cancel watchdog. */ 2175 callout_stop(&sc->tick_ch); 2176 2177 /* 2178 * Clear and disable interrupts. 2179 */ 2180 AE_WRITE_4(sc, AE_IMR_REG, 0); 2181 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2182 2183 /* 2184 * Stop Rx/Tx MACs. 2185 */ 2186 ae_stop_txmac(sc); 2187 ae_stop_rxmac(sc); 2188 2189 /* 2190 * Stop DMA engines. 2191 */ 2192 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2193 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2194 2195 /* 2196 * Wait for everything to enter idle state. 2197 */ 2198 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2199 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2200 break; 2201 DELAY(100); 2202 } 2203 if (i == AE_IDLE_TIMEOUT) 2204 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2205} 2206 2207static void 2208ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2209{ 2210 2211 if ((flags & AE_TXS_BCAST) != 0) 2212 stats->tx_bcast++; 2213 if ((flags & AE_TXS_MCAST) != 0) 2214 stats->tx_mcast++; 2215 if ((flags & AE_TXS_PAUSE) != 0) 2216 stats->tx_pause++; 2217 if ((flags & AE_TXS_CTRL) != 0) 2218 stats->tx_ctrl++; 2219 if ((flags & AE_TXS_DEFER) != 0) 2220 stats->tx_defer++; 2221 if ((flags & AE_TXS_EXCDEFER) != 0) 2222 stats->tx_excdefer++; 2223 if ((flags & AE_TXS_SINGLECOL) != 0) 2224 stats->tx_singlecol++; 2225 if ((flags & AE_TXS_MULTICOL) != 0) 2226 stats->tx_multicol++; 2227 if ((flags & AE_TXS_LATECOL) != 0) 2228 stats->tx_latecol++; 2229 if ((flags & AE_TXS_ABORTCOL) != 0) 2230 stats->tx_abortcol++; 2231 if ((flags & AE_TXS_UNDERRUN) != 0) 2232 stats->tx_underrun++; 2233} 2234 2235static void 2236ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2237{ 2238 2239 if ((flags & AE_RXD_BCAST) != 0) 2240 stats->rx_bcast++; 2241 if ((flags & AE_RXD_MCAST) != 0) 2242 stats->rx_mcast++; 2243 if ((flags & AE_RXD_PAUSE) != 0) 2244 stats->rx_pause++; 2245 if ((flags & AE_RXD_CTRL) != 0) 2246 stats->rx_ctrl++; 2247 if ((flags & AE_RXD_CRCERR) != 0) 2248 stats->rx_crcerr++; 2249 if ((flags & AE_RXD_CODEERR) != 0) 2250 stats->rx_codeerr++; 2251 if ((flags & AE_RXD_RUNT) != 0) 2252 stats->rx_runt++; 2253 if ((flags & AE_RXD_FRAG) != 0) 2254 stats->rx_frag++; 2255 if ((flags & AE_RXD_TRUNC) != 0) 2256 stats->rx_trunc++; 2257 if ((flags & AE_RXD_ALIGN) != 0) 2258 stats->rx_align++; 2259} 2260