1/****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33******************************************************************************/ 34/*$FreeBSD$*/ 35 36#ifndef _E1000_HW_H_ 37#define _E1000_HW_H_ 38 39#include "e1000_osdep.h" 40#include "e1000_regs.h" 41#include "e1000_defines.h" 42 43struct e1000_hw; 44 45#define E1000_DEV_ID_82542 0x1000 46#define E1000_DEV_ID_82543GC_FIBER 0x1001 47#define E1000_DEV_ID_82543GC_COPPER 0x1004 48#define E1000_DEV_ID_82544EI_COPPER 0x1008 49#define E1000_DEV_ID_82544EI_FIBER 0x1009 50#define E1000_DEV_ID_82544GC_COPPER 0x100C 51#define E1000_DEV_ID_82544GC_LOM 0x100D 52#define E1000_DEV_ID_82540EM 0x100E 53#define E1000_DEV_ID_82540EM_LOM 0x1015 54#define E1000_DEV_ID_82540EP_LOM 0x1016 55#define E1000_DEV_ID_82540EP 0x1017 56#define E1000_DEV_ID_82540EP_LP 0x101E 57#define E1000_DEV_ID_82545EM_COPPER 0x100F 58#define E1000_DEV_ID_82545EM_FIBER 0x1011 59#define E1000_DEV_ID_82545GM_COPPER 0x1026 60#define E1000_DEV_ID_82545GM_FIBER 0x1027 61#define E1000_DEV_ID_82545GM_SERDES 0x1028 62#define E1000_DEV_ID_82546EB_COPPER 0x1010 63#define E1000_DEV_ID_82546EB_FIBER 0x1012 64#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 65#define E1000_DEV_ID_82546GB_COPPER 0x1079 66#define E1000_DEV_ID_82546GB_FIBER 0x107A 67#define E1000_DEV_ID_82546GB_SERDES 0x107B 68#define E1000_DEV_ID_82546GB_PCIE 0x108A 69#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 71#define E1000_DEV_ID_82541EI 0x1013 72#define E1000_DEV_ID_82541EI_MOBILE 0x1018 73#define E1000_DEV_ID_82541ER_LOM 0x1014 74#define E1000_DEV_ID_82541ER 0x1078 75#define E1000_DEV_ID_82541GI 0x1076 76#define E1000_DEV_ID_82541GI_LF 0x107C 77#define E1000_DEV_ID_82541GI_MOBILE 0x1077 78#define E1000_DEV_ID_82547EI 0x1019 79#define E1000_DEV_ID_82547EI_MOBILE 0x101A 80#define E1000_DEV_ID_82547GI 0x1075 81#define E1000_DEV_ID_82571EB_COPPER 0x105E 82#define E1000_DEV_ID_82571EB_FIBER 0x105F 83#define E1000_DEV_ID_82571EB_SERDES 0x1060 84#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 85#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 86#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 87#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 88#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 89#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 90#define E1000_DEV_ID_82572EI_COPPER 0x107D 91#define E1000_DEV_ID_82572EI_FIBER 0x107E 92#define E1000_DEV_ID_82572EI_SERDES 0x107F 93#define E1000_DEV_ID_82572EI 0x10B9 94#define E1000_DEV_ID_82573E 0x108B 95#define E1000_DEV_ID_82573E_IAMT 0x108C 96#define E1000_DEV_ID_82573L 0x109A 97#define E1000_DEV_ID_82574L 0x10D3 98#define E1000_DEV_ID_82574LA 0x10F6 99#define E1000_DEV_ID_82583V 0x150C 100#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104#define E1000_DEV_ID_ICH8_82567V_3 0x1501 105#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107#define E1000_DEV_ID_ICH8_IGP_C 0x104B 108#define E1000_DEV_ID_ICH8_IFE 0x104C 109#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111#define E1000_DEV_ID_ICH8_IGP_M 0x104D 112#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116#define E1000_DEV_ID_ICH9_BM 0x10E5 117#define E1000_DEV_ID_ICH9_IGP_C 0x294C 118#define E1000_DEV_ID_ICH9_IFE 0x10C0 119#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131#define E1000_DEV_ID_PCH2_LV_LM 0x1502 132#define E1000_DEV_ID_PCH2_LV_V 0x1503 133#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138#define E1000_DEV_ID_PCH_I218_V2 0x15A1 139#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 159#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 160#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 161#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 162#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 163#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 164#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 165#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 166#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 167#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 168#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 169#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 170#define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 171#define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 172#define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 173#define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 174#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 175#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 176#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 177#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 178#define E1000_DEV_ID_82576 0x10C9 179#define E1000_DEV_ID_82576_FIBER 0x10E6 180#define E1000_DEV_ID_82576_SERDES 0x10E7 181#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 182#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 183#define E1000_DEV_ID_82576_NS 0x150A 184#define E1000_DEV_ID_82576_NS_SERDES 0x1518 185#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 186#define E1000_DEV_ID_82576_VF 0x10CA 187#define E1000_DEV_ID_82576_VF_HV 0x152D 188#define E1000_DEV_ID_I350_VF 0x1520 189#define E1000_DEV_ID_I350_VF_HV 0x152F 190#define E1000_DEV_ID_82575EB_COPPER 0x10A7 191#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 192#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 193#define E1000_DEV_ID_82580_COPPER 0x150E 194#define E1000_DEV_ID_82580_FIBER 0x150F 195#define E1000_DEV_ID_82580_SERDES 0x1510 196#define E1000_DEV_ID_82580_SGMII 0x1511 197#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 198#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 199#define E1000_DEV_ID_I350_COPPER 0x1521 200#define E1000_DEV_ID_I350_FIBER 0x1522 201#define E1000_DEV_ID_I350_SERDES 0x1523 202#define E1000_DEV_ID_I350_SGMII 0x1524 203#define E1000_DEV_ID_I350_DA4 0x1546 204#define E1000_DEV_ID_I210_COPPER 0x1533 205#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 206#define E1000_DEV_ID_I210_COPPER_IT 0x1535 207#define E1000_DEV_ID_I210_FIBER 0x1536 208#define E1000_DEV_ID_I210_SERDES 0x1537 209#define E1000_DEV_ID_I210_SGMII 0x1538 210#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 211#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 212#define E1000_DEV_ID_I210_SGMII_FLASHLESS 0x15F6 213#define E1000_DEV_ID_I211_COPPER 0x1539 214#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 215#define E1000_DEV_ID_I354_SGMII 0x1F41 216#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 217#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 218#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 219#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 220#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 221 222#define E1000_REVISION_0 0 223#define E1000_REVISION_1 1 224#define E1000_REVISION_2 2 225#define E1000_REVISION_3 3 226#define E1000_REVISION_4 4 227 228#define E1000_FUNC_0 0 229#define E1000_FUNC_1 1 230#define E1000_FUNC_2 2 231#define E1000_FUNC_3 3 232 233#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 234#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 235#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 236#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 237 238enum e1000_mac_type { 239 e1000_undefined = 0, 240 e1000_82542, 241 e1000_82543, 242 e1000_82544, 243 e1000_82540, 244 e1000_82545, 245 e1000_82545_rev_3, 246 e1000_82546, 247 e1000_82546_rev_3, 248 e1000_82541, 249 e1000_82541_rev_2, 250 e1000_82547, 251 e1000_82547_rev_2, 252 e1000_82571, 253 e1000_82572, 254 e1000_82573, 255 e1000_82574, 256 e1000_82583, 257 e1000_80003es2lan, 258 e1000_ich8lan, 259 e1000_ich9lan, 260 e1000_ich10lan, 261 e1000_pchlan, 262 e1000_pch2lan, 263 e1000_pch_lpt, 264 e1000_pch_spt, 265 e1000_pch_cnp, 266 e1000_pch_tgp, 267 e1000_pch_adp, 268 e1000_pch_mtp, 269 e1000_82575, 270 e1000_82576, 271 e1000_82580, 272 e1000_i350, 273 e1000_i354, 274 e1000_i210, 275 e1000_i211, 276 e1000_vfadapt, 277 e1000_vfadapt_i350, 278 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 279}; 280 281enum e1000_media_type { 282 e1000_media_type_unknown = 0, 283 e1000_media_type_copper = 1, 284 e1000_media_type_fiber = 2, 285 e1000_media_type_internal_serdes = 3, 286 e1000_num_media_types 287}; 288 289enum e1000_nvm_type { 290 e1000_nvm_unknown = 0, 291 e1000_nvm_none, 292 e1000_nvm_eeprom_spi, 293 e1000_nvm_eeprom_microwire, 294 e1000_nvm_flash_hw, 295 e1000_nvm_invm, 296 e1000_nvm_flash_sw 297}; 298 299enum e1000_nvm_override { 300 e1000_nvm_override_none = 0, 301 e1000_nvm_override_spi_small, 302 e1000_nvm_override_spi_large, 303 e1000_nvm_override_microwire_small, 304 e1000_nvm_override_microwire_large 305}; 306 307enum e1000_phy_type { 308 e1000_phy_unknown = 0, 309 e1000_phy_none, 310 e1000_phy_m88, 311 e1000_phy_igp, 312 e1000_phy_igp_2, 313 e1000_phy_gg82563, 314 e1000_phy_igp_3, 315 e1000_phy_ife, 316 e1000_phy_bm, 317 e1000_phy_82578, 318 e1000_phy_82577, 319 e1000_phy_82579, 320 e1000_phy_i217, 321 e1000_phy_82580, 322 e1000_phy_vf, 323 e1000_phy_i210, 324}; 325 326enum e1000_bus_type { 327 e1000_bus_type_unknown = 0, 328 e1000_bus_type_pci, 329 e1000_bus_type_pcix, 330 e1000_bus_type_pci_express, 331 e1000_bus_type_reserved 332}; 333 334enum e1000_bus_speed { 335 e1000_bus_speed_unknown = 0, 336 e1000_bus_speed_33, 337 e1000_bus_speed_66, 338 e1000_bus_speed_100, 339 e1000_bus_speed_120, 340 e1000_bus_speed_133, 341 e1000_bus_speed_2500, 342 e1000_bus_speed_5000, 343 e1000_bus_speed_reserved 344}; 345 346enum e1000_bus_width { 347 e1000_bus_width_unknown = 0, 348 e1000_bus_width_pcie_x1, 349 e1000_bus_width_pcie_x2, 350 e1000_bus_width_pcie_x4 = 4, 351 e1000_bus_width_pcie_x8 = 8, 352 e1000_bus_width_32, 353 e1000_bus_width_64, 354 e1000_bus_width_reserved 355}; 356 357enum e1000_1000t_rx_status { 358 e1000_1000t_rx_status_not_ok = 0, 359 e1000_1000t_rx_status_ok, 360 e1000_1000t_rx_status_undefined = 0xFF 361}; 362 363enum e1000_rev_polarity { 364 e1000_rev_polarity_normal = 0, 365 e1000_rev_polarity_reversed, 366 e1000_rev_polarity_undefined = 0xFF 367}; 368 369enum e1000_fc_mode { 370 e1000_fc_none = 0, 371 e1000_fc_rx_pause, 372 e1000_fc_tx_pause, 373 e1000_fc_full, 374 e1000_fc_default = 0xFF 375}; 376 377enum e1000_ffe_config { 378 e1000_ffe_config_enabled = 0, 379 e1000_ffe_config_active, 380 e1000_ffe_config_blocked 381}; 382 383enum e1000_dsp_config { 384 e1000_dsp_config_disabled = 0, 385 e1000_dsp_config_enabled, 386 e1000_dsp_config_activated, 387 e1000_dsp_config_undefined = 0xFF 388}; 389 390enum e1000_ms_type { 391 e1000_ms_hw_default = 0, 392 e1000_ms_force_master, 393 e1000_ms_force_slave, 394 e1000_ms_auto 395}; 396 397enum e1000_smart_speed { 398 e1000_smart_speed_default = 0, 399 e1000_smart_speed_on, 400 e1000_smart_speed_off 401}; 402 403enum e1000_serdes_link_state { 404 e1000_serdes_link_down = 0, 405 e1000_serdes_link_autoneg_progress, 406 e1000_serdes_link_autoneg_complete, 407 e1000_serdes_link_forced_up 408}; 409 410#define __le16 u16 411#define __le32 u32 412#define __le64 u64 413/* Receive Descriptor */ 414struct e1000_rx_desc { 415 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 416 __le16 length; /* Length of data DMAed into data buffer */ 417 __le16 csum; /* Packet checksum */ 418 u8 status; /* Descriptor status */ 419 u8 errors; /* Descriptor Errors */ 420 __le16 special; 421}; 422 423/* Receive Descriptor - Extended */ 424union e1000_rx_desc_extended { 425 struct { 426 __le64 buffer_addr; 427 __le64 reserved; 428 } read; 429 struct { 430 struct { 431 __le32 mrq; /* Multiple Rx Queues */ 432 union { 433 __le32 rss; /* RSS Hash */ 434 struct { 435 __le16 ip_id; /* IP id */ 436 __le16 csum; /* Packet Checksum */ 437 } csum_ip; 438 } hi_dword; 439 } lower; 440 struct { 441 __le32 status_error; /* ext status/error */ 442 __le16 length; 443 __le16 vlan; /* VLAN tag */ 444 } upper; 445 } wb; /* writeback */ 446}; 447 448#define MAX_PS_BUFFERS 4 449 450/* Number of packet split data buffers (not including the header buffer) */ 451#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 452 453/* Receive Descriptor - Packet Split */ 454union e1000_rx_desc_packet_split { 455 struct { 456 /* one buffer for protocol header(s), three data buffers */ 457 __le64 buffer_addr[MAX_PS_BUFFERS]; 458 } read; 459 struct { 460 struct { 461 __le32 mrq; /* Multiple Rx Queues */ 462 union { 463 __le32 rss; /* RSS Hash */ 464 struct { 465 __le16 ip_id; /* IP id */ 466 __le16 csum; /* Packet Checksum */ 467 } csum_ip; 468 } hi_dword; 469 } lower; 470 struct { 471 __le32 status_error; /* ext status/error */ 472 __le16 length0; /* length of buffer 0 */ 473 __le16 vlan; /* VLAN tag */ 474 } middle; 475 struct { 476 __le16 header_status; 477 /* length of buffers 1-3 */ 478 __le16 length[PS_PAGE_BUFFERS]; 479 } upper; 480 __le64 reserved; 481 } wb; /* writeback */ 482}; 483 484/* Transmit Descriptor */ 485struct e1000_tx_desc { 486 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 487 union { 488 __le32 data; 489 struct { 490 __le16 length; /* Data buffer length */ 491 u8 cso; /* Checksum offset */ 492 u8 cmd; /* Descriptor control */ 493 } flags; 494 } lower; 495 union { 496 __le32 data; 497 struct { 498 u8 status; /* Descriptor status */ 499 u8 css; /* Checksum start */ 500 __le16 special; 501 } fields; 502 } upper; 503}; 504 505/* Offload Context Descriptor */ 506struct e1000_context_desc { 507 union { 508 __le32 ip_config; 509 struct { 510 u8 ipcss; /* IP checksum start */ 511 u8 ipcso; /* IP checksum offset */ 512 __le16 ipcse; /* IP checksum end */ 513 } ip_fields; 514 } lower_setup; 515 union { 516 __le32 tcp_config; 517 struct { 518 u8 tucss; /* TCP checksum start */ 519 u8 tucso; /* TCP checksum offset */ 520 __le16 tucse; /* TCP checksum end */ 521 } tcp_fields; 522 } upper_setup; 523 __le32 cmd_and_length; 524 union { 525 __le32 data; 526 struct { 527 u8 status; /* Descriptor status */ 528 u8 hdr_len; /* Header length */ 529 __le16 mss; /* Maximum segment size */ 530 } fields; 531 } tcp_seg_setup; 532}; 533 534/* Offload data descriptor */ 535struct e1000_data_desc { 536 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 537 union { 538 __le32 data; 539 struct { 540 __le16 length; /* Data buffer length */ 541 u8 typ_len_ext; 542 u8 cmd; 543 } flags; 544 } lower; 545 union { 546 __le32 data; 547 struct { 548 u8 status; /* Descriptor status */ 549 u8 popts; /* Packet Options */ 550 __le16 special; 551 } fields; 552 } upper; 553}; 554 555/* Statistics counters collected by the MAC */ 556struct e1000_hw_stats { 557 u64 crcerrs; 558 u64 algnerrc; 559 u64 symerrs; 560 u64 rxerrc; 561 u64 mpc; 562 u64 scc; 563 u64 ecol; 564 u64 mcc; 565 u64 latecol; 566 u64 colc; 567 u64 dc; 568 u64 tncrs; 569 u64 sec; 570 u64 cexterr; 571 u64 rlec; 572 u64 xonrxc; 573 u64 xontxc; 574 u64 xoffrxc; 575 u64 xofftxc; 576 u64 fcruc; 577 u64 prc64; 578 u64 prc127; 579 u64 prc255; 580 u64 prc511; 581 u64 prc1023; 582 u64 prc1522; 583 u64 gprc; 584 u64 bprc; 585 u64 mprc; 586 u64 gptc; 587 u64 gorc; 588 u64 gotc; 589 u64 rnbc; 590 u64 ruc; 591 u64 rfc; 592 u64 roc; 593 u64 rjc; 594 u64 mgprc; 595 u64 mgpdc; 596 u64 mgptc; 597 u64 tor; 598 u64 tot; 599 u64 tpr; 600 u64 tpt; 601 u64 ptc64; 602 u64 ptc127; 603 u64 ptc255; 604 u64 ptc511; 605 u64 ptc1023; 606 u64 ptc1522; 607 u64 mptc; 608 u64 bptc; 609 u64 tsctc; 610 u64 tsctfc; 611 u64 iac; 612 u64 icrxptc; 613 u64 icrxatc; 614 u64 ictxptc; 615 u64 ictxatc; 616 u64 ictxqec; 617 u64 ictxqmtc; 618 u64 icrxdmtc; 619 u64 icrxoc; 620 u64 cbtmpc; 621 u64 htdpmc; 622 u64 cbrdpc; 623 u64 cbrmpc; 624 u64 rpthc; 625 u64 hgptc; 626 u64 htcbdpc; 627 u64 hgorc; 628 u64 hgotc; 629 u64 lenerrs; 630 u64 scvpc; 631 u64 hrmpc; 632 u64 doosync; 633 u64 o2bgptc; 634 u64 o2bspc; 635 u64 b2ospc; 636 u64 b2ogprc; 637}; 638 639struct e1000_vf_stats { 640 u64 base_gprc; 641 u64 base_gptc; 642 u64 base_gorc; 643 u64 base_gotc; 644 u64 base_mprc; 645 u64 base_gotlbc; 646 u64 base_gptlbc; 647 u64 base_gorlbc; 648 u64 base_gprlbc; 649 650 u32 last_gprc; 651 u32 last_gptc; 652 u32 last_gorc; 653 u32 last_gotc; 654 u32 last_mprc; 655 u32 last_gotlbc; 656 u32 last_gptlbc; 657 u32 last_gorlbc; 658 u32 last_gprlbc; 659 660 u64 gprc; 661 u64 gptc; 662 u64 gorc; 663 u64 gotc; 664 u64 mprc; 665 u64 gotlbc; 666 u64 gptlbc; 667 u64 gorlbc; 668 u64 gprlbc; 669}; 670 671struct e1000_phy_stats { 672 u32 idle_errors; 673 u32 receive_errors; 674}; 675 676struct e1000_host_mng_dhcp_cookie { 677 u32 signature; 678 u8 status; 679 u8 reserved0; 680 u16 vlan_id; 681 u32 reserved1; 682 u16 reserved2; 683 u8 reserved3; 684 u8 checksum; 685}; 686 687/* Host Interface "Rev 1" */ 688struct e1000_host_command_header { 689 u8 command_id; 690 u8 command_length; 691 u8 command_options; 692 u8 checksum; 693}; 694 695#define E1000_HI_MAX_DATA_LENGTH 252 696struct e1000_host_command_info { 697 struct e1000_host_command_header command_header; 698 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 699}; 700 701/* Host Interface "Rev 2" */ 702struct e1000_host_mng_command_header { 703 u8 command_id; 704 u8 checksum; 705 u16 reserved1; 706 u16 reserved2; 707 u16 command_length; 708}; 709 710#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 711struct e1000_host_mng_command_info { 712 struct e1000_host_mng_command_header command_header; 713 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 714}; 715 716#include "e1000_mac.h" 717#include "e1000_phy.h" 718#include "e1000_nvm.h" 719#include "e1000_manage.h" 720#include "e1000_mbx.h" 721 722/* Function pointers for the MAC. */ 723struct e1000_mac_operations { 724 s32 (*init_params)(struct e1000_hw *); 725 s32 (*id_led_init)(struct e1000_hw *); 726 s32 (*blink_led)(struct e1000_hw *); 727 bool (*check_mng_mode)(struct e1000_hw *); 728 s32 (*check_for_link)(struct e1000_hw *); 729 s32 (*cleanup_led)(struct e1000_hw *); 730 void (*clear_hw_cntrs)(struct e1000_hw *); 731 void (*clear_vfta)(struct e1000_hw *); 732 s32 (*get_bus_info)(struct e1000_hw *); 733 void (*set_lan_id)(struct e1000_hw *); 734 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 735 s32 (*led_on)(struct e1000_hw *); 736 s32 (*led_off)(struct e1000_hw *); 737 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 738 s32 (*reset_hw)(struct e1000_hw *); 739 s32 (*init_hw)(struct e1000_hw *); 740 void (*shutdown_serdes)(struct e1000_hw *); 741 void (*power_up_serdes)(struct e1000_hw *); 742 s32 (*setup_link)(struct e1000_hw *); 743 s32 (*setup_physical_interface)(struct e1000_hw *); 744 s32 (*setup_led)(struct e1000_hw *); 745 void (*write_vfta)(struct e1000_hw *, u32, u32); 746 void (*config_collision_dist)(struct e1000_hw *); 747 int (*rar_set)(struct e1000_hw *, u8*, u32); 748 s32 (*read_mac_addr)(struct e1000_hw *); 749 s32 (*validate_mdi_setting)(struct e1000_hw *); 750 s32 (*set_obff_timer)(struct e1000_hw *, u32); 751 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 752 void (*release_swfw_sync)(struct e1000_hw *, u16); 753}; 754 755/* When to use various PHY register access functions: 756 * 757 * Func Caller 758 * Function Does Does When to use 759 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 760 * X_reg L,P,A n/a for simple PHY reg accesses 761 * X_reg_locked P,A L for multiple accesses of different regs 762 * on different pages 763 * X_reg_page A L,P for multiple accesses of different regs 764 * on the same page 765 * 766 * Where X=[read|write], L=locking, P=sets page, A=register access 767 * 768 */ 769struct e1000_phy_operations { 770 s32 (*init_params)(struct e1000_hw *); 771 s32 (*acquire)(struct e1000_hw *); 772 s32 (*cfg_on_link_up)(struct e1000_hw *); 773 s32 (*check_polarity)(struct e1000_hw *); 774 s32 (*check_reset_block)(struct e1000_hw *); 775 s32 (*commit)(struct e1000_hw *); 776 s32 (*force_speed_duplex)(struct e1000_hw *); 777 s32 (*get_cfg_done)(struct e1000_hw *hw); 778 s32 (*get_cable_length)(struct e1000_hw *); 779 s32 (*get_info)(struct e1000_hw *); 780 s32 (*set_page)(struct e1000_hw *, u16); 781 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 782 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 783 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 784 void (*release)(struct e1000_hw *); 785 s32 (*reset)(struct e1000_hw *); 786 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 787 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 788 s32 (*write_reg)(struct e1000_hw *, u32, u16); 789 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 790 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 791 void (*power_up)(struct e1000_hw *); 792 void (*power_down)(struct e1000_hw *); 793 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 794 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 795}; 796 797/* Function pointers for the NVM. */ 798struct e1000_nvm_operations { 799 s32 (*init_params)(struct e1000_hw *); 800 s32 (*acquire)(struct e1000_hw *); 801 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 802 void (*release)(struct e1000_hw *); 803 void (*reload)(struct e1000_hw *); 804 s32 (*update)(struct e1000_hw *); 805 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 806 s32 (*validate)(struct e1000_hw *); 807 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 808}; 809 810struct e1000_mac_info { 811 struct e1000_mac_operations ops; 812 u8 addr[ETHER_ADDR_LEN]; 813 u8 perm_addr[ETHER_ADDR_LEN]; 814 815 enum e1000_mac_type type; 816 817 u32 collision_delta; 818 u32 ledctl_default; 819 u32 ledctl_mode1; 820 u32 ledctl_mode2; 821 u32 mc_filter_type; 822 u32 tx_packet_delta; 823 u32 txcw; 824 825 u16 current_ifs_val; 826 u16 ifs_max_val; 827 u16 ifs_min_val; 828 u16 ifs_ratio; 829 u16 ifs_step_size; 830 u16 mta_reg_count; 831 u16 uta_reg_count; 832 833 /* Maximum size of the MTA register table in all supported adapters */ 834#define MAX_MTA_REG 128 835 u32 mta_shadow[MAX_MTA_REG]; 836 u16 rar_entry_count; 837 838 u8 forced_speed_duplex; 839 840 bool adaptive_ifs; 841 bool has_fwsm; 842 bool arc_subsystem_valid; 843 bool asf_firmware_present; 844 bool autoneg; 845 bool autoneg_failed; 846 bool get_link_status; 847 bool in_ifs_mode; 848 bool report_tx_early; 849 enum e1000_serdes_link_state serdes_link_state; 850 bool serdes_has_link; 851 bool tx_pkt_filtering; 852 u32 max_frame_size; 853}; 854 855struct e1000_phy_info { 856 struct e1000_phy_operations ops; 857 enum e1000_phy_type type; 858 859 enum e1000_1000t_rx_status local_rx; 860 enum e1000_1000t_rx_status remote_rx; 861 enum e1000_ms_type ms_type; 862 enum e1000_ms_type original_ms_type; 863 enum e1000_rev_polarity cable_polarity; 864 enum e1000_smart_speed smart_speed; 865 866 u32 addr; 867 u32 id; 868 u32 reset_delay_us; /* in usec */ 869 u32 revision; 870 871 enum e1000_media_type media_type; 872 873 u16 autoneg_advertised; 874 u16 autoneg_mask; 875 u16 cable_length; 876 u16 max_cable_length; 877 u16 min_cable_length; 878 879 u8 mdix; 880 881 bool disable_polarity_correction; 882 bool is_mdix; 883 bool polarity_correction; 884 bool speed_downgraded; 885 bool autoneg_wait_to_complete; 886}; 887 888struct e1000_nvm_info { 889 struct e1000_nvm_operations ops; 890 enum e1000_nvm_type type; 891 enum e1000_nvm_override override; 892 893 u32 flash_bank_size; 894 u32 flash_base_addr; 895 896 u16 word_size; 897 u16 delay_usec; 898 u16 address_bits; 899 u16 opcode_bits; 900 u16 page_size; 901}; 902 903struct e1000_bus_info { 904 enum e1000_bus_type type; 905 enum e1000_bus_speed speed; 906 enum e1000_bus_width width; 907 908 u16 func; 909 u16 pci_cmd_word; 910}; 911 912struct e1000_fc_info { 913 u32 high_water; /* Flow control high-water mark */ 914 u32 low_water; /* Flow control low-water mark */ 915 u16 pause_time; /* Flow control pause timer */ 916 u16 refresh_time; /* Flow control refresh timer */ 917 bool send_xon; /* Flow control send XON */ 918 bool strict_ieee; /* Strict IEEE mode */ 919 enum e1000_fc_mode current_mode; /* FC mode in effect */ 920 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 921}; 922 923struct e1000_mbx_operations { 924 s32 (*init_params)(struct e1000_hw *hw); 925 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 926 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 927 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 928 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 929 s32 (*check_for_msg)(struct e1000_hw *, u16); 930 s32 (*check_for_ack)(struct e1000_hw *, u16); 931 s32 (*check_for_rst)(struct e1000_hw *, u16); 932}; 933 934struct e1000_mbx_stats { 935 u32 msgs_tx; 936 u32 msgs_rx; 937 938 u32 acks; 939 u32 reqs; 940 u32 rsts; 941}; 942 943struct e1000_mbx_info { 944 struct e1000_mbx_operations ops; 945 struct e1000_mbx_stats stats; 946 u32 timeout; 947 u32 usec_delay; 948 u16 size; 949}; 950 951struct e1000_dev_spec_82541 { 952 enum e1000_dsp_config dsp_config; 953 enum e1000_ffe_config ffe_config; 954 u16 spd_default; 955 bool phy_init_script; 956}; 957 958struct e1000_dev_spec_82542 { 959 bool dma_fairness; 960}; 961 962struct e1000_dev_spec_82543 { 963 u32 tbi_compatibility; 964 bool dma_fairness; 965 bool init_phy_disabled; 966}; 967 968struct e1000_dev_spec_82571 { 969 bool laa_is_present; 970 u32 smb_counter; 971}; 972 973struct e1000_dev_spec_80003es2lan { 974 bool mdic_wa_enable; 975}; 976 977struct e1000_shadow_ram { 978 u16 value; 979 bool modified; 980}; 981 982#define E1000_SHADOW_RAM_WORDS 2048 983 984/* I218 PHY Ultra Low Power (ULP) states */ 985enum e1000_ulp_state { 986 e1000_ulp_state_unknown, 987 e1000_ulp_state_off, 988 e1000_ulp_state_on, 989}; 990 991struct e1000_dev_spec_ich8lan { 992 bool kmrn_lock_loss_workaround_enabled; 993 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 994 bool nvm_k1_enabled; 995 bool disable_k1_off; 996 bool eee_disable; 997 u16 eee_lp_ability; 998 enum e1000_ulp_state ulp_state; 999 bool ulp_capability_disabled; 1000 bool during_suspend_flow; 1001 bool smbus_disable; 1002}; 1003 1004struct e1000_dev_spec_82575 { 1005 bool sgmii_active; 1006 bool global_device_reset; 1007 bool eee_disable; 1008 bool module_plugged; 1009 bool clear_semaphore_once; 1010 u32 mtu; 1011 struct sfp_e1000_flags eth_flags; 1012 u8 media_port; 1013 bool media_changed; 1014}; 1015 1016struct e1000_dev_spec_vf { 1017 u32 vf_number; 1018 u32 v2p_mailbox; 1019}; 1020 1021struct e1000_hw { 1022 void *back; 1023 1024 u8 *hw_addr; 1025 u8 *flash_address; 1026 unsigned long io_base; 1027 1028 struct e1000_mac_info mac; 1029 struct e1000_fc_info fc; 1030 struct e1000_phy_info phy; 1031 struct e1000_nvm_info nvm; 1032 struct e1000_bus_info bus; 1033 struct e1000_mbx_info mbx; 1034 struct e1000_host_mng_dhcp_cookie mng_cookie; 1035 1036 union { 1037 struct e1000_dev_spec_82541 _82541; 1038 struct e1000_dev_spec_82542 _82542; 1039 struct e1000_dev_spec_82543 _82543; 1040 struct e1000_dev_spec_82571 _82571; 1041 struct e1000_dev_spec_80003es2lan _80003es2lan; 1042 struct e1000_dev_spec_ich8lan ich8lan; 1043 struct e1000_dev_spec_82575 _82575; 1044 struct e1000_dev_spec_vf vf; 1045 } dev_spec; 1046 1047 u16 device_id; 1048 u16 subsystem_vendor_id; 1049 u16 subsystem_device_id; 1050 u16 vendor_id; 1051 1052 u8 revision_id; 1053}; 1054 1055#include "e1000_82541.h" 1056#include "e1000_82543.h" 1057#include "e1000_82571.h" 1058#include "e1000_80003es2lan.h" 1059#include "e1000_ich8lan.h" 1060#include "e1000_82575.h" 1061#include "e1000_i210.h" 1062#include "e1000_base.h" 1063 1064/* These functions must be implemented by drivers */ 1065void e1000_pci_clear_mwi(struct e1000_hw *hw); 1066void e1000_pci_set_mwi(struct e1000_hw *hw); 1067s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1068s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1069void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1070void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1071 1072#endif 1073