/linux-master/drivers/gpu/drm/panel/ |
H A D | panel-leadtek-ltk050h3146w.c | 319 .clock = 59756, 410 .clock = 64018, 506 .clock = 65595,
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H A D | panel-khadas-ts050.c | 779 .clock = 160000,
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H A D | panel-ilitek-ili9881c.c | 1343 .clock = 62000, 1360 .clock = 69700, 1377 .clock = 62000, 1394 .clock = 59400, 1411 .clock = 64000, 1428 .clock = 67911,
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H A D | panel-jdi-fhd-r63452.c | 187 .clock = (1080 + 120 + 16 + 40) * (1920 + 4 + 2 + 4) * 60 / 1000,
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H A D | panel-edp.c | 1022 .clock = 70589, 1035 .clock = 69300, 1063 .clock = 142600, 1090 .clock = 150660, 1117 .clock = 69500, 1139 .clock = 141000, 1167 .clock = 71900, 1178 .clock = 57500, 1208 .clock = 207800, 1220 .clock [all...] |
/linux-master/drivers/gpu/drm/nouveau/ |
H A D | nouveau_dp.c | 545 unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock; local 556 clock *= 2; 559 mode_rate = DIV_ROUND_UP(clock * bpp, 8); 564 if (ds_max_dotclock && clock > ds_max_dotclock) 567 if (clock < min_clock) 571 *out_clock = clock;
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/linux-master/drivers/gpu/drm/msm/ |
H A D | msm_gpu.c | 75 * Set the clock to a deliberately low rate. On older targets the clock 652 u64 elapsed, clock = 0, cycles; local 662 /* Calculate the clock frequency from the number of CP cycles */ 664 clock = cycles * 1000; 665 do_div(clock, elapsed); 671 trace_msm_gpu_submit_retired(submit, elapsed, clock,
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/linux-master/drivers/gpu/drm/msm/dsi/ |
H A D | dsi_host.c | 207 pr_err("%s: cannot get interface clock\n", __func__); 251 pr_err("%s: can't find src clock. ret=%d\n", 268 pr_err("%s: can't find byte_intf clock. ret=%d\n", 297 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 306 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 315 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 557 pclk_rate = mode->clock * 1000; 565 * the clock rates have to be split between the two dsi controllers. 566 * Adjust the byte and pixel clock rates for each dsi host accordingly. 631 * esc clock i [all...] |
/linux-master/drivers/gpu/drm/msm/dp/ |
H A D | dp_panel.c | 441 drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n", 442 drm_mode->clock);
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H A D | dp_drm.c | 251 int mode_pclk_khz = mode->clock; 260 if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
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H A D | dp_display.c | 923 int mode_pclk_khz = mode->clock; 932 if (mode->clock > DP_MAX_PIXEL_CLK_KHZ) 1503 if (!dp_display->dp_mode.drm_mode.clock) {
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H A D | dp_ctrl.c | 166 /* sync clock & static Mvid */ 968 in.pclk_khz = drm_mode->clock; 1578 * Disable and re-enable the mainlink clock since the 1579 * link clock might have been adjusted as part of the 1722 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1725 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); 1828 pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1956 pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; 1979 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
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H A D | dp_debug.c | 64 seq_printf(seq, "\t\tpixel clock khz = %d\n", 65 drm_mode->clock);
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/linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_encoder.c | 1773 pclk_rate = mode->clock; /* pixel clock in kHz */ 1786 * Line time calculation based on Pixel clock and HTOTAL.
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/linux-master/drivers/gpu/drm/mgag200/ |
H A D | mgag200_mode.c | 798 if (!mode->htotal || !mode->vtotal || !mode->clock) 804 pixels_per_second = active_area * mode->clock * 1000;
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H A D | mgag200_drv.h | 196 int data, clock; member in struct:mga_i2c_chan
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/linux-master/drivers/gpu/drm/meson/ |
H A D | meson_dw_mipi_dsi.c | 81 /* Set the bit clock rate to hs_clk_rate */ 85 dev_err(mipi_dsi->dev, "Failed to set DSI Bit clock rate %lu (ret %d)\n", 90 /* Make sure the rate of the bit clock is not modified by someone else */ 94 "Failed to set the exclusivity on the bit clock rate (ret %d)\n", ret); 99 ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000); 102 dev_err(mipi_dsi->dev, "Failed to set DSI Pixel clock rate %u (%d)\n", 103 mipi_dsi->mode->clock * 1000, ret); 109 dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret); 153 /* Remove the exclusivity on the bit clock rate */ 169 phy_mipi_dphy_get_default_config(mode->clock * 100 [all...] |
/linux-master/drivers/gpu/drm/mediatek/ |
H A D | mtk_hdmi.c | 415 mode->clock == 74250 && 651 unsigned int clock; member in struct:hdmi_acr_n 669 * @clock: rounded TMDS clock in kHz 671 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) argument 677 if (clock == hdmi_rec_n_table[i].clock) 702 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) argument 704 switch (clock) { 714 return clock * 100 749 mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int sample_rate, unsigned int clock) argument 836 mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) argument [all...] |
H A D | mtk_dsi.c | 622 dev_err(dev, "Failed to enable engine clock: %d\n", ret); 628 dev_err(dev, "Failed to enable digital clock: %d\n", ret); 796 if (mode->clock * bpp / dsi->lanes > 1500000) 1115 "Failed to get engine clock\n"); 1121 "Failed to get digital clock\n"); 1125 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
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H A D | mtk_dpi.c | 123 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. 142 unsigned int (*cal_factor)(int clock); 486 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); 492 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); 519 factor = dpi->conf->cal_factor(mode->clock); 523 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", 531 * pixels for each iteration: divide the clock by this number and 546 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", 558 * pixels for each iteration: divide the clock by this number and 750 if (mode->clock > dp 843 mt8173_calculate_factor(int clock) argument 855 mt2701_calculate_factor(int clock) argument 865 mt8183_calculate_factor(int clock) argument 875 mt8195_dpintf_calculate_factor(int clock) argument [all...] |
H A D | mtk_dp.c | 1339 if (mode.clock > 0) 1342 (mode.clock * 4); 1375 mode.clock / 2000 : mode.clock / 1000; 2327 if (rate < mode->clock * bpp / 8) 2380 if ((rate < (mode->clock * 24 / 8)) && 2381 (rate > (mode->clock * 16 / 8)) &&
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H A D | mtk_disp_merge.c | 44 * and the maximum frequency of mmsys clock is 594MHz. 236 if (rate && mode->clock > rate) { 237 dev_dbg(dev, "invalid clock: %d (>%lu)\n", mode->clock, rate); 276 * pixel clock, inversely proportional to vbp). Please adjust the 279 rate = mode->clock / (mode->vtotal - mode->vsync_end); 332 dev_err(dev, "failed to get merge async clock\n");
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/linux-master/drivers/gpu/drm/loongson/ |
H A D | lsdc_crtc.c | 588 seq_printf(m, "Pixel clock required: %d kHz\n", mode->clock); 590 seq_printf(m, "Diff: %d kHz\n", out_khz - mode->clock); 708 drm_printf(p, "\tInput clock divider = %u\n", pparms->div_ref); 709 drm_printf(p, "\tMedium clock multiplier = %u\n", pparms->loopc); 710 drm_printf(p, "\tOutput clock divider = %u\n", pparms->div_out); 756 if (mode->clock > descp->max_pixel_clk) { 757 drm_dbg_kms(ddev, "mode %dx%d, pixel clock=%d is too high\n", 758 mode->hdisplay, mode->vdisplay, mode->clock); 781 unsigned int clock local [all...] |
/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_utils.h | 34 #include <linux/sched/clock.h>
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/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | handlers.c | 452 * So the correct sequence to find DP stream clock is: 456 * Pixel clock = h_total * v_total * refresh_rate 457 * stream clock = Pixel clock 528 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 543 struct dpll clock = {}; local 572 clock.m1 = 2; 573 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 576 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 578 clock [all...] |