Lines Matching refs:clock
207 pr_err("%s: cannot get interface clock\n", __func__);
251 pr_err("%s: can't find src clock. ret=%d\n",
268 pr_err("%s: can't find byte_intf clock. ret=%d\n",
297 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
306 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
315 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
557 pclk_rate = mode->clock * 1000;
565 * the clock rates have to be split between the two dsi controllers.
566 * Adjust the byte and pixel clock rates for each dsi host accordingly.
631 * esc clock is byte clock followed by a 4 bit divider,
632 * we need to find an escape clock frequency within the
634 * We iterate here between an escape clock frequencey
2066 * mdss interrupt is generated in mdp core clock domain
2067 * mdp clock need to be enabled to receive dsi interrupt
2300 /* CPHY transmits 16 bits over 7 clock cycles
2332 /* TODO: clock should be turned off for command mode,