Lines Matching refs:clock
123 * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
142 unsigned int (*cal_factor)(int clock);
486 dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
492 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
519 factor = dpi->conf->cal_factor(mode->clock);
523 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
531 * pixels for each iteration: divide the clock by this number and
546 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
558 * pixels for each iteration: divide the clock by this number and
750 if (mode->clock > dpi->conf->max_clock_khz)
843 static unsigned int mt8173_calculate_factor(int clock)
845 if (clock <= 27000)
847 else if (clock <= 84000)
849 else if (clock <= 167000)
855 static unsigned int mt2701_calculate_factor(int clock)
857 if (clock <= 64000)
859 else if (clock <= 128000)
865 static unsigned int mt8183_calculate_factor(int clock)
867 if (clock <= 27000)
869 else if (clock <= 167000)
875 static unsigned int mt8195_dpintf_calculate_factor(int clock)
877 if (clock < 70000)
879 else if (clock < 200000)
1042 "Failed to get engine clock\n");
1047 "Failed to get pixel clock\n");
1052 "Failed to get tvdpll clock\n");