Searched refs:reg_offset (Results 276 - 300 of 376) sorted by relevance

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/linux-master/sound/soc/amd/acp/
H A Dacp-platform.c145 stream->reg_offset = 0x02000000;
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Dsta_ioctl.c1244 u32 reg_offset, u32 reg_value)
1249 reg_rw.offset = reg_offset;
1263 u32 reg_offset, u32 *value)
1269 reg_rw.offset = reg_offset;
1243 mwifiex_reg_write(struct mwifiex_private *priv, u32 reg_type, u32 reg_offset, u32 reg_value) argument
1262 mwifiex_reg_read(struct mwifiex_private *priv, u32 reg_type, u32 reg_offset, u32 *value) argument
/linux-master/drivers/platform/x86/intel/pmc/
H A Dcore.c58 static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset) argument
60 return readl(pmc->regbase + reg_offset);
63 static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset, argument
66 writel(val, pmc->regbase + reg_offset);
/linux-master/drivers/crypto/hisilicon/sec2/
H A Dsec_main.c295 .reg_offset = SEC_DFX_BASE,
298 .reg_offset = SEC_DFX_COMMON1,
301 .reg_offset = SEC_DFX_COMMON2,
304 .reg_offset = SEC_DFX_CORE,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu.h511 uint32_t reg_offset; member in struct:amdgpu_allowed_register_entry
578 u32 sh_num, u32 reg_offset, u32 *value);
670 u32 reg_offset; member in struct:amdgpu_mmio_remap
1064 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; member in struct:amdgpu_device
H A Dsdma_v5_0.c173 base = adev->reg_offset[GC_HWIP][0][1];
177 base = adev->reg_offset[GC_HWIP][0][0];
1529 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? local
1533 sdma_cntl = RREG32(reg_offset);
1536 WREG32(reg_offset, sdma_cntl);
H A Dsdma_v6_0.c71 base = adev->reg_offset[GC_HWIP][0][1];
75 base = adev->reg_offset[GC_HWIP][0][0];
1402 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); local
1405 sdma_cntl = RREG32(reg_offset);
1408 WREG32(reg_offset, sdma_cntl);
H A Dmes_v10_1.c304 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
306 adev->reg_offset[MMHUB_HWIP][0][i];
308 adev->reg_offset[OSSSYS_HWIP][0][i];
/linux-master/drivers/tty/serial/
H A Dmxs-auart.c360 const u16 *reg_offset; member in struct:vendor_data
407 .reg_offset = mxs_asm9260_offsets,
411 .reg_offset = mxs_stmp37xx_offsets,
476 return uap->vendor->reg_offset[reg];
/linux-master/sound/soc/sh/rcar/
H A Dgen.c38 unsigned int reg_offset; member in struct:rsnd_regmap_field_conf
46 .reg_offset = offset, \
200 regf.reg = conf[i].reg_offset;
/linux-master/include/linux/
H A Dregmap.h1489 * @reg_offset: Offset of the status/mask register within the bank
1494 unsigned int reg_offset; member in struct:regmap_irq
1500 [_irq] = { .reg_offset = (_off), .mask = (_mask) }
1505 .reg_offset = (_id) / (_reg_bits), \
/linux-master/drivers/net/ethernet/marvell/
H A Dmvneta.c1638 unsigned int reg_offset; local
1647 reg_offset = last_nibble % 4;
1653 unicast_reg &= ~(0xff << (8 * reg_offset));
1655 unicast_reg &= ~(0xff << (8 * reg_offset));
1656 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
3077 unsigned int reg_offset; local
3082 reg_offset = last_byte % 4;
3088 smc_table_reg &= ~(0xff << (8 * reg_offset));
3090 smc_table_reg &= ~(0xff << (8 * reg_offset));
3091 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
3112 unsigned int reg_offset; local
[all...]
/linux-master/drivers/net/wireless/intel/iwlegacy/
H A D3945.c2567 u32 reg_offset; local
2591 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2592 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2593 reg_offset += sizeof(u32), image++)
2594 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
/linux-master/drivers/i2c/busses/
H A Di2c-tegra.c979 u32 val, reg, dma_burst, reg_offset; local
996 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
998 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1007 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1009 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c718 u32 reg_offset; local
747 reg_offset = (blk->addr - itcm_base) >> 2;
749 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
752 reg_offset = (blk->addr - dtcm_base) >> 2;
754 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
/linux-master/drivers/phy/cadence/
H A Dphy-cadence-sierra.c66 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
68 (((ln) << 9) << (reg_offset)))
210 #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
212 (((ln) << 8) << (reg_offset)))
222 #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
224 (((ln) << 8) << (reg_offset)))
/linux-master/drivers/net/ethernet/broadcom/
H A Dbcmsysport.c433 val = rxchk_readl(priv, s->reg_offset);
435 rxchk_writel(priv, 0, s->reg_offset);
438 val = rbuf_readl(priv, s->reg_offset);
440 rbuf_writel(priv, 0, s->reg_offset);
446 val = rdma_readl(priv, s->reg_offset);
448 rdma_writel(priv, 0, s->reg_offset);
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_cxt.c2181 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; local
2282 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2293 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2328 u32 reg_offset, elem_size, hw_p_size, elems_per_p; local
2394 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2403 reg_offset,
/linux-master/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c471 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) argument
473 void __iomem *address = devinfo->regs + reg_offset;
479 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) argument
481 void __iomem *address = devinfo->regs + reg_offset;
488 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, argument
491 void __iomem *address = devinfo->regs + reg_offset;
/linux-master/drivers/mtd/nand/raw/
H A Drockchip-nand-controller.c336 int reg_offset = nfc->band_offset; local
348 nfc->regs + reg_offset + BANK_CMD);
357 nfc->regs + reg_offset + BANK_ADDR);
/linux-master/drivers/net/ethernet/renesas/
H A Dsh_eth.h532 const u16 *reg_offset; member in struct:sh_eth_private
/linux-master/drivers/crypto/cavium/zip/
H A Dzip_main.c599 zipregs[i].reg_offset));
/linux-master/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c987 u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0; local
999 reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
1001 reg_val = readl(scu->base + reg_offset);
1004 writel(reg_val, scu->base + reg_offset);
/linux-master/drivers/net/ethernet/8390/
H A Dmcf8390.c388 ei_local->reg_offset = offsets;
/linux-master/sound/soc/codecs/
H A Dcs35l45.h457 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \

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