1// SPDX-License-Identifier: GPL-2.0 2/* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9#include <linux/acpi.h> 10#include <linux/bitfield.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/dmaengine.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/i2c.h> 17#include <linux/init.h> 18#include <linux/interrupt.h> 19#include <linux/io.h> 20#include <linux/iopoll.h> 21#include <linux/irq.h> 22#include <linux/kernel.h> 23#include <linux/ktime.h> 24#include <linux/module.h> 25#include <linux/of.h> 26#include <linux/pinctrl/consumer.h> 27#include <linux/platform_device.h> 28#include <linux/pm_runtime.h> 29#include <linux/reset.h> 30 31#define BYTES_PER_FIFO_WORD 4 32 33#define I2C_CNFG 0x000 34#define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) 35#define I2C_CNFG_PACKET_MODE_EN BIT(10) 36#define I2C_CNFG_NEW_MASTER_FSM BIT(11) 37#define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 38#define I2C_STATUS 0x01c 39#define I2C_SL_CNFG 0x020 40#define I2C_SL_CNFG_NACK BIT(1) 41#define I2C_SL_CNFG_NEWSL BIT(2) 42#define I2C_SL_ADDR1 0x02c 43#define I2C_SL_ADDR2 0x030 44#define I2C_TLOW_SEXT 0x034 45#define I2C_TX_FIFO 0x050 46#define I2C_RX_FIFO 0x054 47#define I2C_PACKET_TRANSFER_STATUS 0x058 48#define I2C_FIFO_CONTROL 0x05c 49#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 50#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 51#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 52#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 53#define I2C_FIFO_STATUS 0x060 54#define I2C_FIFO_STATUS_TX GENMASK(7, 4) 55#define I2C_FIFO_STATUS_RX GENMASK(3, 0) 56#define I2C_INT_MASK 0x064 57#define I2C_INT_STATUS 0x068 58#define I2C_INT_BUS_CLR_DONE BIT(11) 59#define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 60#define I2C_INT_NO_ACK BIT(3) 61#define I2C_INT_ARBITRATION_LOST BIT(2) 62#define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 63#define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 64#define I2C_CLK_DIVISOR 0x06c 65#define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) 66#define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) 67 68#define DVC_CTRL_REG1 0x000 69#define DVC_CTRL_REG1_INTR_EN BIT(10) 70#define DVC_CTRL_REG3 0x008 71#define DVC_CTRL_REG3_SW_PROG BIT(26) 72#define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 73#define DVC_STATUS 0x00c 74#define DVC_STATUS_I2C_DONE_INTR BIT(30) 75 76#define I2C_ERR_NONE 0x00 77#define I2C_ERR_NO_ACK BIT(0) 78#define I2C_ERR_ARBITRATION_LOST BIT(1) 79#define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 80#define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 81 82#define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28) 83#define PACKET_HEADER0_PACKET_ID GENMASK(23, 16) 84#define PACKET_HEADER0_CONT_ID GENMASK(15, 12) 85#define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86#define PACKET_HEADER0_PROTOCOL_I2C 1 87 88#define I2C_HEADER_CONT_ON_NAK BIT(21) 89#define I2C_HEADER_READ BIT(19) 90#define I2C_HEADER_10BIT_ADDR BIT(18) 91#define I2C_HEADER_IE_ENABLE BIT(17) 92#define I2C_HEADER_REPEAT_START BIT(16) 93#define I2C_HEADER_CONTINUE_XFER BIT(15) 94#define I2C_HEADER_SLAVE_ADDR_SHIFT 1 95 96#define I2C_BUS_CLEAR_CNFG 0x084 97#define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) 98#define I2C_BC_STOP_COND BIT(2) 99#define I2C_BC_TERMINATE BIT(1) 100#define I2C_BC_ENABLE BIT(0) 101#define I2C_BUS_CLEAR_STATUS 0x088 102#define I2C_BC_STATUS BIT(0) 103 104#define I2C_CONFIG_LOAD 0x08c 105#define I2C_MSTR_CONFIG_LOAD BIT(0) 106 107#define I2C_CLKEN_OVERRIDE 0x090 108#define I2C_MST_CORE_CLKEN_OVR BIT(0) 109 110#define I2C_INTERFACE_TIMING_0 0x094 111#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) 112#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) 113#define I2C_INTERFACE_TIMING_1 0x098 114#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) 115#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 116#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 117#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 118 119#define I2C_HS_INTERFACE_TIMING_0 0x09c 120#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) 121#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) 122#define I2C_HS_INTERFACE_TIMING_1 0x0a0 123#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) 124#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) 125#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) 126 127#define I2C_MST_FIFO_CONTROL 0x0b4 128#define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 129#define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 130#define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 131#define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 132 133#define I2C_MST_FIFO_STATUS 0x0b8 134#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) 135#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 136 137/* configuration load timeout in microseconds */ 138#define I2C_CONFIG_LOAD_TIMEOUT 1000000 139 140/* packet header size in bytes */ 141#define I2C_PACKET_HEADER_SIZE 12 142 143/* 144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 145 * avoid DMA overhead, otherwise external APB DMA controller will be used. 146 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 147 * I2C_PACKET_HEADER_SIZE. 148 */ 149#define I2C_PIO_MODE_PREFERRED_LEN 32 150 151/* 152 * msg_end_type: The bus control which needs to be sent at end of transfer. 153 * @MSG_END_STOP: Send stop pulse. 154 * @MSG_END_REPEAT_START: Send repeat-start. 155 * @MSG_END_CONTINUE: Don't send stop or repeat-start. 156 */ 157enum msg_end_type { 158 MSG_END_STOP, 159 MSG_END_REPEAT_START, 160 MSG_END_CONTINUE, 161}; 162 163/** 164 * struct tegra_i2c_hw_feature : per hardware generation features 165 * @has_continue_xfer_support: continue-transfer supported 166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 167 * completion interrupt on per packet basis. 168 * @has_config_load_reg: Has the config load register to load the new 169 * configuration. 170 * @clk_divisor_hs_mode: Clock divisor in HS mode. 171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 172 * applicable if there is no fast clock source i.e. single clock 173 * source. 174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 175 * applicable if there is no fast clock source i.e. single clock 176 * source. 177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 178 * applicable if there is no fast clock source (i.e. single 179 * clock source). 180 * @has_multi_master_mode: The I2C controller supports running in single-master 181 * or multi-master mode. 182 * @has_slcg_override_reg: The I2C controller supports a register that 183 * overrides the second level clock gating. 184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 185 * provides additional features and allows for longer messages to 186 * be transferred in one go. 187 * @quirks: I2C adapter quirks for limiting write/read transfer size and not 188 * allowing 0 length transfers. 189 * @supports_bus_clear: Bus Clear support to recover from bus hang during 190 * SDA stuck low from device for some unknown reasons. 191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 192 * @tlow_std_mode: Low period of the clock in standard mode. 193 * @thigh_std_mode: High period of the clock in standard mode. 194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 197 * in standard mode. 198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 199 * conditions in fast/fast-plus modes. 200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 201 * in HS mode. 202 * @has_interface_timing_reg: Has interface timing register to program the tuned 203 * timing settings. 204 */ 205struct tegra_i2c_hw_feature { 206 bool has_continue_xfer_support; 207 bool has_per_pkt_xfer_complete_irq; 208 bool has_config_load_reg; 209 u32 clk_divisor_hs_mode; 210 u32 clk_divisor_std_mode; 211 u32 clk_divisor_fast_mode; 212 u32 clk_divisor_fast_plus_mode; 213 bool has_multi_master_mode; 214 bool has_slcg_override_reg; 215 bool has_mst_fifo; 216 const struct i2c_adapter_quirks *quirks; 217 bool supports_bus_clear; 218 bool has_apb_dma; 219 u32 tlow_std_mode; 220 u32 thigh_std_mode; 221 u32 tlow_fast_fastplus_mode; 222 u32 thigh_fast_fastplus_mode; 223 u32 setup_hold_time_std_mode; 224 u32 setup_hold_time_fast_fast_plus_mode; 225 u32 setup_hold_time_hs_mode; 226 bool has_interface_timing_reg; 227}; 228 229/** 230 * struct tegra_i2c_dev - per device I2C context 231 * @dev: device reference for power management 232 * @hw: Tegra I2C HW feature 233 * @adapter: core I2C layer adapter information 234 * @div_clk: clock reference for div clock of I2C controller 235 * @clocks: array of I2C controller clocks 236 * @nclocks: number of clocks in the array 237 * @rst: reset control for the I2C controller 238 * @base: ioremapped registers cookie 239 * @base_phys: physical base address of the I2C controller 240 * @cont_id: I2C controller ID, used for packet header 241 * @irq: IRQ number of transfer complete interrupt 242 * @is_dvc: identifies the DVC I2C controller, has a different register layout 243 * @is_vi: identifies the VI I2C controller, has a different register layout 244 * @msg_complete: transfer completion notifier 245 * @msg_buf_remaining: size of unsent data in the message buffer 246 * @msg_len: length of message in current transfer 247 * @msg_err: error code for completed message 248 * @msg_buf: pointer to current message data 249 * @msg_read: indicates that the transfer is a read access 250 * @timings: i2c timings information like bus frequency 251 * @multimaster_mode: indicates that I2C controller is in multi-master mode 252 * @dma_chan: DMA channel 253 * @dma_phys: handle to DMA resources 254 * @dma_buf: pointer to allocated DMA buffer 255 * @dma_buf_size: DMA buffer size 256 * @dma_mode: indicates active DMA transfer 257 * @dma_complete: DMA completion notifier 258 * @atomic_mode: indicates active atomic transfer 259 */ 260struct tegra_i2c_dev { 261 struct device *dev; 262 struct i2c_adapter adapter; 263 264 const struct tegra_i2c_hw_feature *hw; 265 struct reset_control *rst; 266 unsigned int cont_id; 267 unsigned int irq; 268 269 phys_addr_t base_phys; 270 void __iomem *base; 271 272 struct clk_bulk_data clocks[2]; 273 unsigned int nclocks; 274 275 struct clk *div_clk; 276 struct i2c_timings timings; 277 278 struct completion msg_complete; 279 size_t msg_buf_remaining; 280 unsigned int msg_len; 281 int msg_err; 282 u8 *msg_buf; 283 284 struct completion dma_complete; 285 struct dma_chan *dma_chan; 286 unsigned int dma_buf_size; 287 struct device *dma_dev; 288 dma_addr_t dma_phys; 289 void *dma_buf; 290 291 bool multimaster_mode; 292 bool atomic_mode; 293 bool dma_mode; 294 bool msg_read; 295 bool is_dvc; 296 bool is_vi; 297}; 298 299#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) 300#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) 301 302static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 303 unsigned int reg) 304{ 305 writel_relaxed(val, i2c_dev->base + reg); 306} 307 308static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 309{ 310 return readl_relaxed(i2c_dev->base + reg); 311} 312 313/* 314 * If necessary, i2c_writel() and i2c_readl() will offset the register 315 * in order to talk to the I2C block inside the DVC block. 316 */ 317static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 318{ 319 if (IS_DVC(i2c_dev)) 320 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 321 else if (IS_VI(i2c_dev)) 322 reg = 0xc00 + (reg << 2); 323 324 return reg; 325} 326 327static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) 328{ 329 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 330 331 /* read back register to make sure that register writes completed */ 332 if (reg != I2C_TX_FIFO) 333 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 334 else if (IS_VI(i2c_dev)) 335 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); 336} 337 338static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) 339{ 340 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 341} 342 343static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 344 unsigned int reg, unsigned int len) 345{ 346 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 347} 348 349static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, 350 unsigned int reg, unsigned int len) 351{ 352 u32 *data32 = data; 353 354 /* 355 * VI I2C controller has known hardware bug where writes get stuck 356 * when immediate multiple writes happen to TX_FIFO register. 357 * Recommended software work around is to read I2C register after 358 * each write to TX_FIFO register to flush out the data. 359 */ 360 while (len--) 361 i2c_writel(i2c_dev, *data32++, reg); 362} 363 364static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 365 unsigned int reg, unsigned int len) 366{ 367 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 368} 369 370static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 371{ 372 u32 int_mask; 373 374 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 375 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 376} 377 378static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 379{ 380 u32 int_mask; 381 382 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 383 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 384} 385 386static void tegra_i2c_dma_complete(void *args) 387{ 388 struct tegra_i2c_dev *i2c_dev = args; 389 390 complete(&i2c_dev->dma_complete); 391} 392 393static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 394{ 395 struct dma_async_tx_descriptor *dma_desc; 396 enum dma_transfer_direction dir; 397 398 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 399 400 reinit_completion(&i2c_dev->dma_complete); 401 402 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 403 404 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys, 405 len, dir, DMA_PREP_INTERRUPT | 406 DMA_CTRL_ACK); 407 if (!dma_desc) { 408 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", 409 i2c_dev->msg_read ? "RX" : "TX"); 410 return -EINVAL; 411 } 412 413 dma_desc->callback = tegra_i2c_dma_complete; 414 dma_desc->callback_param = i2c_dev; 415 416 dmaengine_submit(dma_desc); 417 dma_async_issue_pending(i2c_dev->dma_chan); 418 419 return 0; 420} 421 422static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 423{ 424 if (i2c_dev->dma_buf) { 425 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 426 i2c_dev->dma_buf, i2c_dev->dma_phys); 427 i2c_dev->dma_buf = NULL; 428 } 429 430 if (i2c_dev->dma_chan) { 431 dma_release_channel(i2c_dev->dma_chan); 432 i2c_dev->dma_chan = NULL; 433 } 434} 435 436static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 437{ 438 dma_addr_t dma_phys; 439 u32 *dma_buf; 440 int err; 441 442 if (IS_VI(i2c_dev)) 443 return 0; 444 445 if (i2c_dev->hw->has_apb_dma) { 446 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 447 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 448 return 0; 449 } 450 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) { 451 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n"); 452 return 0; 453 } 454 455 /* 456 * The same channel will be used for both RX and TX. 457 * Keeping the name as "tx" for backward compatibility 458 * with existing devicetrees. 459 */ 460 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx"); 461 if (IS_ERR(i2c_dev->dma_chan)) { 462 err = PTR_ERR(i2c_dev->dma_chan); 463 i2c_dev->dma_chan = NULL; 464 goto err_out; 465 } 466 467 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev; 468 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + 469 I2C_PACKET_HEADER_SIZE; 470 471 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, 472 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 473 if (!dma_buf) { 474 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); 475 err = -ENOMEM; 476 goto err_out; 477 } 478 479 i2c_dev->dma_buf = dma_buf; 480 i2c_dev->dma_phys = dma_phys; 481 482 return 0; 483 484err_out: 485 tegra_i2c_release_dma(i2c_dev); 486 if (err != -EPROBE_DEFER) { 487 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 488 dev_err(i2c_dev->dev, "falling back to PIO\n"); 489 return 0; 490 } 491 492 return err; 493} 494 495/* 496 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 497 * block. This block is identical to the rest of the I2C blocks, except that 498 * it only supports master mode, it has registers moved around, and it needs 499 * some extra init to get it into I2C mode. The register moves are handled 500 * by i2c_readl() and i2c_writel(). 501 */ 502static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 503{ 504 u32 val; 505 506 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 507 val |= DVC_CTRL_REG3_SW_PROG; 508 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 509 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 510 511 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 512 val |= DVC_CTRL_REG1_INTR_EN; 513 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 514} 515 516static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) 517{ 518 u32 value; 519 520 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | 521 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); 522 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); 523 524 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | 525 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | 526 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | 527 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); 528 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); 529 530 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | 531 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); 532 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); 533 534 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | 535 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | 536 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); 537 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); 538 539 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; 540 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); 541 542 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); 543} 544 545static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, 546 u32 reg, u32 mask, u32 delay_us, 547 u32 timeout_us) 548{ 549 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); 550 u32 val; 551 552 if (!i2c_dev->atomic_mode) 553 return readl_relaxed_poll_timeout(addr, val, !(val & mask), 554 delay_us, timeout_us); 555 556 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), 557 delay_us, timeout_us); 558} 559 560static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 561{ 562 u32 mask, val, offset; 563 int err; 564 565 if (i2c_dev->hw->has_mst_fifo) { 566 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 567 I2C_MST_FIFO_CONTROL_RX_FLUSH; 568 offset = I2C_MST_FIFO_CONTROL; 569 } else { 570 mask = I2C_FIFO_CONTROL_TX_FLUSH | 571 I2C_FIFO_CONTROL_RX_FLUSH; 572 offset = I2C_FIFO_CONTROL; 573 } 574 575 val = i2c_readl(i2c_dev, offset); 576 val |= mask; 577 i2c_writel(i2c_dev, val, offset); 578 579 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000); 580 if (err) { 581 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); 582 return err; 583 } 584 585 return 0; 586} 587 588static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 589{ 590 int err; 591 592 if (!i2c_dev->hw->has_config_load_reg) 593 return 0; 594 595 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 596 597 err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, 598 1000, I2C_CONFIG_LOAD_TIMEOUT); 599 if (err) { 600 dev_err(i2c_dev->dev, "failed to load config\n"); 601 return err; 602 } 603 604 return 0; 605} 606 607static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 608{ 609 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 610 acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); 611 struct i2c_timings *t = &i2c_dev->timings; 612 int err; 613 614 /* 615 * The reset shouldn't ever fail in practice. The failure will be a 616 * sign of a severe problem that needs to be resolved. Still we don't 617 * want to fail the initialization completely because this may break 618 * kernel boot up since voltage regulators use I2C. Hence, we will 619 * emit a noisy warning on error, which won't stay unnoticed and 620 * won't hose machine entirely. 621 */ 622 if (handle) 623 err = acpi_evaluate_object(handle, "_RST", NULL, NULL); 624 else 625 err = reset_control_reset(i2c_dev->rst); 626 627 WARN_ON_ONCE(err); 628 629 if (IS_DVC(i2c_dev)) 630 tegra_dvc_init(i2c_dev); 631 632 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 633 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); 634 635 if (i2c_dev->hw->has_multi_master_mode) 636 val |= I2C_CNFG_MULTI_MASTER_MODE; 637 638 i2c_writel(i2c_dev, val, I2C_CNFG); 639 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 640 641 if (IS_VI(i2c_dev)) 642 tegra_i2c_vi_init(i2c_dev); 643 644 switch (t->bus_freq_hz) { 645 case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 646 default: 647 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 648 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 649 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 650 651 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 652 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 653 else 654 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 655 break; 656 657 case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 658 tlow = i2c_dev->hw->tlow_std_mode; 659 thigh = i2c_dev->hw->thigh_std_mode; 660 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 661 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 662 break; 663 } 664 665 /* make sure clock divisor programmed correctly */ 666 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, 667 i2c_dev->hw->clk_divisor_hs_mode) | 668 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); 669 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 670 671 if (i2c_dev->hw->has_interface_timing_reg) { 672 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | 673 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); 674 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 675 } 676 677 /* 678 * Configure setup and hold times only when tsu_thd is non-zero. 679 * Otherwise, preserve the chip default values. 680 */ 681 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 682 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 683 684 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 685 686 err = clk_set_rate(i2c_dev->div_clk, 687 t->bus_freq_hz * clk_multiplier); 688 if (err) { 689 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); 690 return err; 691 } 692 693 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { 694 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 695 696 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 697 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 698 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 699 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 700 } 701 702 err = tegra_i2c_flush_fifos(i2c_dev); 703 if (err) 704 return err; 705 706 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 707 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 708 709 err = tegra_i2c_wait_for_config_load(i2c_dev); 710 if (err) 711 return err; 712 713 return 0; 714} 715 716static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 717{ 718 u32 cnfg; 719 720 /* 721 * NACK interrupt is generated before the I2C controller generates 722 * the STOP condition on the bus. So, wait for 2 clock periods 723 * before disabling the controller so that the STOP condition has 724 * been delivered properly. 725 */ 726 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); 727 728 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 729 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 730 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 731 732 return tegra_i2c_wait_for_config_load(i2c_dev); 733} 734 735static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 736{ 737 size_t buf_remaining = i2c_dev->msg_buf_remaining; 738 unsigned int words_to_transfer, rx_fifo_avail; 739 u8 *buf = i2c_dev->msg_buf; 740 u32 val; 741 742 /* 743 * Catch overflow due to message fully sent before the check for 744 * RX FIFO availability. 745 */ 746 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 747 return -EINVAL; 748 749 if (i2c_dev->hw->has_mst_fifo) { 750 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 751 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); 752 } else { 753 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 754 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val); 755 } 756 757 /* round down to exclude partial word at the end of buffer */ 758 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 759 if (words_to_transfer > rx_fifo_avail) 760 words_to_transfer = rx_fifo_avail; 761 762 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 763 764 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 765 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 766 rx_fifo_avail -= words_to_transfer; 767 768 /* 769 * If there is a partial word at the end of buffer, handle it 770 * manually to prevent overwriting past the end of buffer. 771 */ 772 if (rx_fifo_avail > 0 && buf_remaining > 0) { 773 /* 774 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 775 * when (words_to_transfer was > rx_fifo_avail) earlier 776 * in this function. 777 */ 778 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 779 val = cpu_to_le32(val); 780 memcpy(buf, &val, buf_remaining); 781 buf_remaining = 0; 782 rx_fifo_avail--; 783 } 784 785 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 786 if (WARN_ON_ONCE(rx_fifo_avail)) 787 return -EINVAL; 788 789 i2c_dev->msg_buf_remaining = buf_remaining; 790 i2c_dev->msg_buf = buf; 791 792 return 0; 793} 794 795static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 796{ 797 size_t buf_remaining = i2c_dev->msg_buf_remaining; 798 unsigned int words_to_transfer, tx_fifo_avail; 799 u8 *buf = i2c_dev->msg_buf; 800 u32 val; 801 802 if (i2c_dev->hw->has_mst_fifo) { 803 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 804 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); 805 } else { 806 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 807 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val); 808 } 809 810 /* round down to exclude partial word at the end of buffer */ 811 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 812 813 /* 814 * This hunk pushes 4 bytes at a time into the TX FIFO. 815 * 816 * It's very common to have < 4 bytes, hence there is no word 817 * to push if we have less than 4 bytes to transfer. 818 */ 819 if (words_to_transfer) { 820 if (words_to_transfer > tx_fifo_avail) 821 words_to_transfer = tx_fifo_avail; 822 823 /* 824 * Update state before writing to FIFO. Note that this may 825 * cause us to finish writing all bytes (AKA buf_remaining 826 * goes to 0), hence we have a potential for an interrupt 827 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt 828 * is disabled at this point. 829 */ 830 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 831 tx_fifo_avail -= words_to_transfer; 832 833 i2c_dev->msg_buf_remaining = buf_remaining; 834 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; 835 836 if (IS_VI(i2c_dev)) 837 i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 838 else 839 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 840 841 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 842 } 843 844 /* 845 * If there is a partial word at the end of buffer, handle it manually 846 * to prevent reading past the end of buffer, which could cross a page 847 * boundary and fault. 848 */ 849 if (tx_fifo_avail > 0 && buf_remaining > 0) { 850 /* 851 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 852 * when (words_to_transfer was > tx_fifo_avail) earlier 853 * in this function for non-zero words_to_transfer. 854 */ 855 memcpy(&val, buf, buf_remaining); 856 val = le32_to_cpu(val); 857 858 i2c_dev->msg_buf_remaining = 0; 859 i2c_dev->msg_buf = NULL; 860 861 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 862 } 863 864 return 0; 865} 866 867static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 868{ 869 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 870 struct tegra_i2c_dev *i2c_dev = dev_id; 871 u32 status; 872 873 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 874 875 if (status == 0) { 876 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", 877 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 878 i2c_readl(i2c_dev, I2C_STATUS), 879 i2c_readl(i2c_dev, I2C_CNFG)); 880 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 881 goto err; 882 } 883 884 if (status & status_err) { 885 tegra_i2c_disable_packet_mode(i2c_dev); 886 if (status & I2C_INT_NO_ACK) 887 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 888 if (status & I2C_INT_ARBITRATION_LOST) 889 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 890 goto err; 891 } 892 893 /* 894 * I2C transfer is terminated during the bus clear, so skip 895 * processing the other interrupts. 896 */ 897 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 898 goto err; 899 900 if (!i2c_dev->dma_mode) { 901 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 902 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 903 /* 904 * Overflow error condition: message fully sent, 905 * with no XFER_COMPLETE interrupt but hardware 906 * asks to transfer more. 907 */ 908 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 909 goto err; 910 } 911 } 912 913 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 914 if (i2c_dev->msg_buf_remaining) 915 tegra_i2c_fill_tx_fifo(i2c_dev); 916 else 917 tegra_i2c_mask_irq(i2c_dev, 918 I2C_INT_TX_FIFO_DATA_REQ); 919 } 920 } 921 922 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 923 if (IS_DVC(i2c_dev)) 924 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 925 926 /* 927 * During message read XFER_COMPLETE interrupt is triggered prior to 928 * DMA completion and during message write XFER_COMPLETE interrupt is 929 * triggered after DMA completion. 930 * 931 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer, 932 * so forcing msg_buf_remaining to 0 in DMA mode. 933 */ 934 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 935 if (i2c_dev->dma_mode) 936 i2c_dev->msg_buf_remaining = 0; 937 /* 938 * Underflow error condition: XFER_COMPLETE before message 939 * fully sent. 940 */ 941 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 942 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 943 goto err; 944 } 945 complete(&i2c_dev->msg_complete); 946 } 947 goto done; 948err: 949 /* mask all interrupts on error */ 950 tegra_i2c_mask_irq(i2c_dev, 951 I2C_INT_NO_ACK | 952 I2C_INT_ARBITRATION_LOST | 953 I2C_INT_PACKET_XFER_COMPLETE | 954 I2C_INT_TX_FIFO_DATA_REQ | 955 I2C_INT_RX_FIFO_DATA_REQ); 956 957 if (i2c_dev->hw->supports_bus_clear) 958 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 959 960 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 961 962 if (IS_DVC(i2c_dev)) 963 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 964 965 if (i2c_dev->dma_mode) { 966 dmaengine_terminate_async(i2c_dev->dma_chan); 967 complete(&i2c_dev->dma_complete); 968 } 969 970 complete(&i2c_dev->msg_complete); 971done: 972 return IRQ_HANDLED; 973} 974 975static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 976 size_t len) 977{ 978 struct dma_slave_config slv_config = {0}; 979 u32 val, reg, dma_burst, reg_offset; 980 int err; 981 982 if (i2c_dev->hw->has_mst_fifo) 983 reg = I2C_MST_FIFO_CONTROL; 984 else 985 reg = I2C_FIFO_CONTROL; 986 987 if (i2c_dev->dma_mode) { 988 if (len & 0xF) 989 dma_burst = 1; 990 else if (len & 0x10) 991 dma_burst = 4; 992 else 993 dma_burst = 8; 994 995 if (i2c_dev->msg_read) { 996 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 997 998 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 999 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1000 slv_config.src_maxburst = dma_burst; 1001 1002 if (i2c_dev->hw->has_mst_fifo) 1003 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 1004 else 1005 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 1006 } else { 1007 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 1008 1009 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 1010 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1011 slv_config.dst_maxburst = dma_burst; 1012 1013 if (i2c_dev->hw->has_mst_fifo) 1014 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 1015 else 1016 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 1017 } 1018 1019 slv_config.device_fc = true; 1020 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config); 1021 if (err) { 1022 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); 1023 dev_err(i2c_dev->dev, "falling back to PIO\n"); 1024 1025 tegra_i2c_release_dma(i2c_dev); 1026 i2c_dev->dma_mode = false; 1027 } else { 1028 goto out; 1029 } 1030 } 1031 1032 if (i2c_dev->hw->has_mst_fifo) 1033 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 1034 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 1035 else 1036 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 1037 I2C_FIFO_CONTROL_RX_TRIG(1); 1038out: 1039 i2c_writel(i2c_dev, val, reg); 1040} 1041 1042static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev, 1043 struct completion *complete, 1044 unsigned int timeout_ms) 1045{ 1046 ktime_t ktime = ktime_get(); 1047 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 1048 1049 do { 1050 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1051 1052 if (status) 1053 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1054 1055 if (completion_done(complete)) { 1056 s64 delta = ktime_ms_delta(ktimeout, ktime); 1057 1058 return msecs_to_jiffies(delta) ?: 1; 1059 } 1060 1061 ktime = ktime_get(); 1062 1063 } while (ktime_before(ktime, ktimeout)); 1064 1065 return 0; 1066} 1067 1068static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev, 1069 struct completion *complete, 1070 unsigned int timeout_ms) 1071{ 1072 unsigned long ret; 1073 1074 if (i2c_dev->atomic_mode) { 1075 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms); 1076 } else { 1077 enable_irq(i2c_dev->irq); 1078 ret = wait_for_completion_timeout(complete, 1079 msecs_to_jiffies(timeout_ms)); 1080 disable_irq(i2c_dev->irq); 1081 1082 /* 1083 * Under some rare circumstances (like running KASAN + 1084 * NFS root) CPU, which handles interrupt, may stuck in 1085 * uninterruptible state for a significant time. In this 1086 * case we will get timeout if I2C transfer is running on 1087 * a sibling CPU, despite of IRQ being raised. 1088 * 1089 * In order to handle this rare condition, the IRQ status 1090 * needs to be checked after timeout. 1091 */ 1092 if (ret == 0) 1093 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0); 1094 } 1095 1096 return ret; 1097} 1098 1099static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1100{ 1101 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1102 u32 val, time_left; 1103 int err; 1104 1105 reinit_completion(&i2c_dev->msg_complete); 1106 1107 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | 1108 I2C_BC_TERMINATE; 1109 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1110 1111 err = tegra_i2c_wait_for_config_load(i2c_dev); 1112 if (err) 1113 return err; 1114 1115 val |= I2C_BC_ENABLE; 1116 i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); 1117 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1118 1119 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); 1120 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1121 1122 if (time_left == 0) { 1123 dev_err(i2c_dev->dev, "failed to clear bus\n"); 1124 return -ETIMEDOUT; 1125 } 1126 1127 val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1128 if (!(val & I2C_BC_STATUS)) { 1129 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); 1130 return -EIO; 1131 } 1132 1133 return -EAGAIN; 1134} 1135 1136static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev, 1137 struct i2c_msg *msg, 1138 enum msg_end_type end_state) 1139{ 1140 u32 *dma_buf = i2c_dev->dma_buf; 1141 u32 packet_header; 1142 1143 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) | 1144 FIELD_PREP(PACKET_HEADER0_PROTOCOL, 1145 PACKET_HEADER0_PROTOCOL_I2C) | 1146 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | 1147 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1); 1148 1149 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1150 *dma_buf++ = packet_header; 1151 else 1152 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1153 1154 packet_header = i2c_dev->msg_len - 1; 1155 1156 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1157 *dma_buf++ = packet_header; 1158 else 1159 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1160 1161 packet_header = I2C_HEADER_IE_ENABLE; 1162 1163 if (end_state == MSG_END_CONTINUE) 1164 packet_header |= I2C_HEADER_CONTINUE_XFER; 1165 else if (end_state == MSG_END_REPEAT_START) 1166 packet_header |= I2C_HEADER_REPEAT_START; 1167 1168 if (msg->flags & I2C_M_TEN) { 1169 packet_header |= msg->addr; 1170 packet_header |= I2C_HEADER_10BIT_ADDR; 1171 } else { 1172 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1173 } 1174 1175 if (msg->flags & I2C_M_IGNORE_NAK) 1176 packet_header |= I2C_HEADER_CONT_ON_NAK; 1177 1178 if (msg->flags & I2C_M_RD) 1179 packet_header |= I2C_HEADER_READ; 1180 1181 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1182 *dma_buf++ = packet_header; 1183 else 1184 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1185} 1186 1187static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, 1188 struct i2c_msg *msg) 1189{ 1190 if (i2c_dev->msg_err == I2C_ERR_NONE) 1191 return 0; 1192 1193 tegra_i2c_init(i2c_dev); 1194 1195 /* start recovery upon arbitration loss in single master mode */ 1196 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1197 if (!i2c_dev->multimaster_mode) 1198 return i2c_recover_bus(&i2c_dev->adapter); 1199 1200 return -EAGAIN; 1201 } 1202 1203 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1204 if (msg->flags & I2C_M_IGNORE_NAK) 1205 return 0; 1206 1207 return -EREMOTEIO; 1208 } 1209 1210 return -EIO; 1211} 1212 1213static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1214 struct i2c_msg *msg, 1215 enum msg_end_type end_state) 1216{ 1217 unsigned long time_left, xfer_time = 100; 1218 size_t xfer_size; 1219 u32 int_mask; 1220 int err; 1221 1222 err = tegra_i2c_flush_fifos(i2c_dev); 1223 if (err) 1224 return err; 1225 1226 i2c_dev->msg_buf = msg->buf; 1227 i2c_dev->msg_len = msg->len; 1228 1229 i2c_dev->msg_err = I2C_ERR_NONE; 1230 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); 1231 reinit_completion(&i2c_dev->msg_complete); 1232 1233 /* 1234 * For SMBUS block read command, read only 1 byte in the first transfer. 1235 * Adjust that 1 byte for the next transfer in the msg buffer and msg 1236 * length. 1237 */ 1238 if (msg->flags & I2C_M_RECV_LEN) { 1239 if (end_state == MSG_END_CONTINUE) { 1240 i2c_dev->msg_len = 1; 1241 } else { 1242 i2c_dev->msg_buf += 1; 1243 i2c_dev->msg_len -= 1; 1244 } 1245 } 1246 1247 i2c_dev->msg_buf_remaining = i2c_dev->msg_len; 1248 1249 if (i2c_dev->msg_read) 1250 xfer_size = i2c_dev->msg_len; 1251 else 1252 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE; 1253 1254 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1255 1256 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && 1257 i2c_dev->dma_buf && !i2c_dev->atomic_mode; 1258 1259 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1260 1261 /* 1262 * Transfer time in mSec = Total bits / transfer rate 1263 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1264 */ 1265 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1266 i2c_dev->timings.bus_freq_hz); 1267 1268 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1269 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1270 1271 if (i2c_dev->dma_mode) { 1272 if (i2c_dev->msg_read) { 1273 dma_sync_single_for_device(i2c_dev->dma_dev, 1274 i2c_dev->dma_phys, 1275 xfer_size, DMA_FROM_DEVICE); 1276 1277 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1278 if (err) 1279 return err; 1280 } else { 1281 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1282 i2c_dev->dma_phys, 1283 xfer_size, DMA_TO_DEVICE); 1284 } 1285 } 1286 1287 tegra_i2c_push_packet_header(i2c_dev, msg, end_state); 1288 1289 if (!i2c_dev->msg_read) { 1290 if (i2c_dev->dma_mode) { 1291 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, 1292 msg->buf, i2c_dev->msg_len); 1293 1294 dma_sync_single_for_device(i2c_dev->dma_dev, 1295 i2c_dev->dma_phys, 1296 xfer_size, DMA_TO_DEVICE); 1297 1298 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1299 if (err) 1300 return err; 1301 } else { 1302 tegra_i2c_fill_tx_fifo(i2c_dev); 1303 } 1304 } 1305 1306 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1307 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1308 1309 if (!i2c_dev->dma_mode) { 1310 if (msg->flags & I2C_M_RD) 1311 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1312 else if (i2c_dev->msg_buf_remaining) 1313 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1314 } 1315 1316 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1317 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", 1318 i2c_readl(i2c_dev, I2C_INT_MASK)); 1319 1320 if (i2c_dev->dma_mode) { 1321 time_left = tegra_i2c_wait_completion(i2c_dev, 1322 &i2c_dev->dma_complete, 1323 xfer_time); 1324 1325 /* 1326 * Synchronize DMA first, since dmaengine_terminate_sync() 1327 * performs synchronization after the transfer's termination 1328 * and we want to get a completion if transfer succeeded. 1329 */ 1330 dmaengine_synchronize(i2c_dev->dma_chan); 1331 dmaengine_terminate_sync(i2c_dev->dma_chan); 1332 1333 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1334 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); 1335 tegra_i2c_init(i2c_dev); 1336 return -ETIMEDOUT; 1337 } 1338 1339 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1340 dma_sync_single_for_cpu(i2c_dev->dma_dev, 1341 i2c_dev->dma_phys, 1342 xfer_size, DMA_FROM_DEVICE); 1343 1344 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); 1345 } 1346 } 1347 1348 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 1349 xfer_time); 1350 1351 tegra_i2c_mask_irq(i2c_dev, int_mask); 1352 1353 if (time_left == 0) { 1354 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); 1355 tegra_i2c_init(i2c_dev); 1356 return -ETIMEDOUT; 1357 } 1358 1359 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1360 time_left, completion_done(&i2c_dev->msg_complete), 1361 i2c_dev->msg_err); 1362 1363 i2c_dev->dma_mode = false; 1364 1365 err = tegra_i2c_error_recover(i2c_dev, msg); 1366 if (err) 1367 return err; 1368 1369 return 0; 1370} 1371 1372static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1373 int num) 1374{ 1375 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1376 int i, ret; 1377 1378 ret = pm_runtime_get_sync(i2c_dev->dev); 1379 if (ret < 0) { 1380 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1381 pm_runtime_put_noidle(i2c_dev->dev); 1382 return ret; 1383 } 1384 1385 for (i = 0; i < num; i++) { 1386 enum msg_end_type end_type = MSG_END_STOP; 1387 1388 if (i < (num - 1)) { 1389 /* check whether follow up message is coming */ 1390 if (msgs[i + 1].flags & I2C_M_NOSTART) 1391 end_type = MSG_END_CONTINUE; 1392 else 1393 end_type = MSG_END_REPEAT_START; 1394 } 1395 /* If M_RECV_LEN use ContinueXfer to read the first byte */ 1396 if (msgs[i].flags & I2C_M_RECV_LEN) { 1397 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE); 1398 if (ret) 1399 break; 1400 /* Set the msg length from first byte */ 1401 msgs[i].len += msgs[i].buf[0]; 1402 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len); 1403 } 1404 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1405 if (ret) 1406 break; 1407 } 1408 1409 pm_runtime_put(i2c_dev->dev); 1410 1411 return ret ?: i; 1412} 1413 1414static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1415 struct i2c_msg msgs[], int num) 1416{ 1417 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1418 int ret; 1419 1420 i2c_dev->atomic_mode = true; 1421 ret = tegra_i2c_xfer(adap, msgs, num); 1422 i2c_dev->atomic_mode = false; 1423 1424 return ret; 1425} 1426 1427static u32 tegra_i2c_func(struct i2c_adapter *adap) 1428{ 1429 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1430 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1431 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1432 1433 if (i2c_dev->hw->has_continue_xfer_support) 1434 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1435 1436 return ret; 1437} 1438 1439static const struct i2c_algorithm tegra_i2c_algo = { 1440 .master_xfer = tegra_i2c_xfer, 1441 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1442 .functionality = tegra_i2c_func, 1443}; 1444 1445/* payload size is only 12 bit */ 1446static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1447 .flags = I2C_AQ_NO_ZERO_LEN, 1448 .max_read_len = SZ_4K, 1449 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1450}; 1451 1452static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1453 .flags = I2C_AQ_NO_ZERO_LEN, 1454 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1455}; 1456 1457static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1458 .recover_bus = tegra_i2c_issue_bus_clear, 1459}; 1460 1461static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1462 .has_continue_xfer_support = false, 1463 .has_per_pkt_xfer_complete_irq = false, 1464 .clk_divisor_hs_mode = 3, 1465 .clk_divisor_std_mode = 0, 1466 .clk_divisor_fast_mode = 0, 1467 .clk_divisor_fast_plus_mode = 0, 1468 .has_config_load_reg = false, 1469 .has_multi_master_mode = false, 1470 .has_slcg_override_reg = false, 1471 .has_mst_fifo = false, 1472 .quirks = &tegra_i2c_quirks, 1473 .supports_bus_clear = false, 1474 .has_apb_dma = true, 1475 .tlow_std_mode = 0x4, 1476 .thigh_std_mode = 0x2, 1477 .tlow_fast_fastplus_mode = 0x4, 1478 .thigh_fast_fastplus_mode = 0x2, 1479 .setup_hold_time_std_mode = 0x0, 1480 .setup_hold_time_fast_fast_plus_mode = 0x0, 1481 .setup_hold_time_hs_mode = 0x0, 1482 .has_interface_timing_reg = false, 1483}; 1484 1485static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1486 .has_continue_xfer_support = true, 1487 .has_per_pkt_xfer_complete_irq = false, 1488 .clk_divisor_hs_mode = 3, 1489 .clk_divisor_std_mode = 0, 1490 .clk_divisor_fast_mode = 0, 1491 .clk_divisor_fast_plus_mode = 0, 1492 .has_config_load_reg = false, 1493 .has_multi_master_mode = false, 1494 .has_slcg_override_reg = false, 1495 .has_mst_fifo = false, 1496 .quirks = &tegra_i2c_quirks, 1497 .supports_bus_clear = false, 1498 .has_apb_dma = true, 1499 .tlow_std_mode = 0x4, 1500 .thigh_std_mode = 0x2, 1501 .tlow_fast_fastplus_mode = 0x4, 1502 .thigh_fast_fastplus_mode = 0x2, 1503 .setup_hold_time_std_mode = 0x0, 1504 .setup_hold_time_fast_fast_plus_mode = 0x0, 1505 .setup_hold_time_hs_mode = 0x0, 1506 .has_interface_timing_reg = false, 1507}; 1508 1509static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1510 .has_continue_xfer_support = true, 1511 .has_per_pkt_xfer_complete_irq = true, 1512 .clk_divisor_hs_mode = 1, 1513 .clk_divisor_std_mode = 0x19, 1514 .clk_divisor_fast_mode = 0x19, 1515 .clk_divisor_fast_plus_mode = 0x10, 1516 .has_config_load_reg = false, 1517 .has_multi_master_mode = false, 1518 .has_slcg_override_reg = false, 1519 .has_mst_fifo = false, 1520 .quirks = &tegra_i2c_quirks, 1521 .supports_bus_clear = true, 1522 .has_apb_dma = true, 1523 .tlow_std_mode = 0x4, 1524 .thigh_std_mode = 0x2, 1525 .tlow_fast_fastplus_mode = 0x4, 1526 .thigh_fast_fastplus_mode = 0x2, 1527 .setup_hold_time_std_mode = 0x0, 1528 .setup_hold_time_fast_fast_plus_mode = 0x0, 1529 .setup_hold_time_hs_mode = 0x0, 1530 .has_interface_timing_reg = false, 1531}; 1532 1533static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1534 .has_continue_xfer_support = true, 1535 .has_per_pkt_xfer_complete_irq = true, 1536 .clk_divisor_hs_mode = 1, 1537 .clk_divisor_std_mode = 0x19, 1538 .clk_divisor_fast_mode = 0x19, 1539 .clk_divisor_fast_plus_mode = 0x10, 1540 .has_config_load_reg = true, 1541 .has_multi_master_mode = false, 1542 .has_slcg_override_reg = true, 1543 .has_mst_fifo = false, 1544 .quirks = &tegra_i2c_quirks, 1545 .supports_bus_clear = true, 1546 .has_apb_dma = true, 1547 .tlow_std_mode = 0x4, 1548 .thigh_std_mode = 0x2, 1549 .tlow_fast_fastplus_mode = 0x4, 1550 .thigh_fast_fastplus_mode = 0x2, 1551 .setup_hold_time_std_mode = 0x0, 1552 .setup_hold_time_fast_fast_plus_mode = 0x0, 1553 .setup_hold_time_hs_mode = 0x0, 1554 .has_interface_timing_reg = true, 1555}; 1556 1557static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1558 .has_continue_xfer_support = true, 1559 .has_per_pkt_xfer_complete_irq = true, 1560 .clk_divisor_hs_mode = 1, 1561 .clk_divisor_std_mode = 0x19, 1562 .clk_divisor_fast_mode = 0x19, 1563 .clk_divisor_fast_plus_mode = 0x10, 1564 .has_config_load_reg = true, 1565 .has_multi_master_mode = false, 1566 .has_slcg_override_reg = true, 1567 .has_mst_fifo = false, 1568 .quirks = &tegra_i2c_quirks, 1569 .supports_bus_clear = true, 1570 .has_apb_dma = true, 1571 .tlow_std_mode = 0x4, 1572 .thigh_std_mode = 0x2, 1573 .tlow_fast_fastplus_mode = 0x4, 1574 .thigh_fast_fastplus_mode = 0x2, 1575 .setup_hold_time_std_mode = 0, 1576 .setup_hold_time_fast_fast_plus_mode = 0, 1577 .setup_hold_time_hs_mode = 0, 1578 .has_interface_timing_reg = true, 1579}; 1580 1581static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1582 .has_continue_xfer_support = true, 1583 .has_per_pkt_xfer_complete_irq = true, 1584 .clk_divisor_hs_mode = 1, 1585 .clk_divisor_std_mode = 0x16, 1586 .clk_divisor_fast_mode = 0x19, 1587 .clk_divisor_fast_plus_mode = 0x10, 1588 .has_config_load_reg = true, 1589 .has_multi_master_mode = false, 1590 .has_slcg_override_reg = true, 1591 .has_mst_fifo = false, 1592 .quirks = &tegra_i2c_quirks, 1593 .supports_bus_clear = true, 1594 .has_apb_dma = false, 1595 .tlow_std_mode = 0x4, 1596 .thigh_std_mode = 0x3, 1597 .tlow_fast_fastplus_mode = 0x4, 1598 .thigh_fast_fastplus_mode = 0x2, 1599 .setup_hold_time_std_mode = 0, 1600 .setup_hold_time_fast_fast_plus_mode = 0, 1601 .setup_hold_time_hs_mode = 0, 1602 .has_interface_timing_reg = true, 1603}; 1604 1605static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1606 .has_continue_xfer_support = true, 1607 .has_per_pkt_xfer_complete_irq = true, 1608 .clk_divisor_hs_mode = 1, 1609 .clk_divisor_std_mode = 0x4f, 1610 .clk_divisor_fast_mode = 0x3c, 1611 .clk_divisor_fast_plus_mode = 0x16, 1612 .has_config_load_reg = true, 1613 .has_multi_master_mode = true, 1614 .has_slcg_override_reg = true, 1615 .has_mst_fifo = true, 1616 .quirks = &tegra194_i2c_quirks, 1617 .supports_bus_clear = true, 1618 .has_apb_dma = false, 1619 .tlow_std_mode = 0x8, 1620 .thigh_std_mode = 0x7, 1621 .tlow_fast_fastplus_mode = 0x2, 1622 .thigh_fast_fastplus_mode = 0x2, 1623 .setup_hold_time_std_mode = 0x08080808, 1624 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1625 .setup_hold_time_hs_mode = 0x090909, 1626 .has_interface_timing_reg = true, 1627}; 1628 1629static const struct of_device_id tegra_i2c_of_match[] = { 1630 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1631 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1632#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 1633 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, }, 1634#endif 1635 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1636 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1637 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1638 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1639 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1640#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) 1641 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1642#endif 1643 {}, 1644}; 1645MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1646 1647static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1648{ 1649 struct device_node *np = i2c_dev->dev->of_node; 1650 bool multi_mode; 1651 1652 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); 1653 1654 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master"); 1655 i2c_dev->multimaster_mode = multi_mode; 1656 1657 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 1658 of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) 1659 i2c_dev->is_dvc = true; 1660 1661 if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && 1662 of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) 1663 i2c_dev->is_vi = true; 1664} 1665 1666static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) 1667{ 1668 if (ACPI_HANDLE(i2c_dev->dev)) 1669 return 0; 1670 1671 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); 1672 if (IS_ERR(i2c_dev->rst)) 1673 return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), 1674 "failed to get reset control\n"); 1675 1676 return 0; 1677} 1678 1679static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) 1680{ 1681 int err; 1682 1683 if (ACPI_HANDLE(i2c_dev->dev)) 1684 return 0; 1685 1686 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; 1687 1688 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) 1689 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; 1690 1691 if (IS_VI(i2c_dev)) 1692 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; 1693 1694 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, 1695 i2c_dev->clocks); 1696 if (err) 1697 return err; 1698 1699 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); 1700 if (err) 1701 return err; 1702 1703 i2c_dev->div_clk = i2c_dev->clocks[0].clk; 1704 1705 if (!i2c_dev->multimaster_mode) 1706 return 0; 1707 1708 err = clk_enable(i2c_dev->div_clk); 1709 if (err) { 1710 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); 1711 goto unprepare_clocks; 1712 } 1713 1714 return 0; 1715 1716unprepare_clocks: 1717 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1718 1719 return err; 1720} 1721 1722static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev) 1723{ 1724 if (i2c_dev->multimaster_mode) 1725 clk_disable(i2c_dev->div_clk); 1726 1727 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); 1728} 1729 1730static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev) 1731{ 1732 int ret; 1733 1734 ret = pm_runtime_get_sync(i2c_dev->dev); 1735 if (ret < 0) 1736 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); 1737 else 1738 ret = tegra_i2c_init(i2c_dev); 1739 1740 pm_runtime_put_sync(i2c_dev->dev); 1741 1742 return ret; 1743} 1744 1745static int tegra_i2c_probe(struct platform_device *pdev) 1746{ 1747 struct tegra_i2c_dev *i2c_dev; 1748 struct resource *res; 1749 int err; 1750 1751 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1752 if (!i2c_dev) 1753 return -ENOMEM; 1754 1755 platform_set_drvdata(pdev, i2c_dev); 1756 1757 init_completion(&i2c_dev->msg_complete); 1758 init_completion(&i2c_dev->dma_complete); 1759 1760 i2c_dev->hw = device_get_match_data(&pdev->dev); 1761 i2c_dev->cont_id = pdev->id; 1762 i2c_dev->dev = &pdev->dev; 1763 1764 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1765 if (IS_ERR(i2c_dev->base)) 1766 return PTR_ERR(i2c_dev->base); 1767 1768 i2c_dev->base_phys = res->start; 1769 1770 err = platform_get_irq(pdev, 0); 1771 if (err < 0) 1772 return err; 1773 1774 i2c_dev->irq = err; 1775 1776 /* interrupt will be enabled during of transfer time */ 1777 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1778 1779 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq, 1780 NULL, tegra_i2c_isr, 1781 IRQF_NO_SUSPEND | IRQF_ONESHOT, 1782 dev_name(i2c_dev->dev), i2c_dev); 1783 if (err) 1784 return err; 1785 1786 tegra_i2c_parse_dt(i2c_dev); 1787 1788 err = tegra_i2c_init_reset(i2c_dev); 1789 if (err) 1790 return err; 1791 1792 err = tegra_i2c_init_clocks(i2c_dev); 1793 if (err) 1794 return err; 1795 1796 err = tegra_i2c_init_dma(i2c_dev); 1797 if (err) 1798 goto release_clocks; 1799 1800 /* 1801 * VI I2C is in VE power domain which is not always ON and not 1802 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a 1803 * non IRQ-safe domain because this prevents powering off the power 1804 * domain. 1805 * 1806 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't 1807 * be used for atomic transfers. 1808 */ 1809 if (!IS_VI(i2c_dev)) 1810 pm_runtime_irq_safe(i2c_dev->dev); 1811 1812 pm_runtime_enable(i2c_dev->dev); 1813 1814 err = tegra_i2c_init_hardware(i2c_dev); 1815 if (err) 1816 goto release_rpm; 1817 1818 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1819 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1820 i2c_dev->adapter.dev.parent = i2c_dev->dev; 1821 i2c_dev->adapter.retries = 1; 1822 i2c_dev->adapter.timeout = 6 * HZ; 1823 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1824 i2c_dev->adapter.owner = THIS_MODULE; 1825 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1826 i2c_dev->adapter.algo = &tegra_i2c_algo; 1827 i2c_dev->adapter.nr = pdev->id; 1828 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1829 1830 if (i2c_dev->hw->supports_bus_clear) 1831 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1832 1833 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1834 sizeof(i2c_dev->adapter.name)); 1835 1836 err = i2c_add_numbered_adapter(&i2c_dev->adapter); 1837 if (err) 1838 goto release_rpm; 1839 1840 return 0; 1841 1842release_rpm: 1843 pm_runtime_disable(i2c_dev->dev); 1844 1845 tegra_i2c_release_dma(i2c_dev); 1846release_clocks: 1847 tegra_i2c_release_clocks(i2c_dev); 1848 1849 return err; 1850} 1851 1852static void tegra_i2c_remove(struct platform_device *pdev) 1853{ 1854 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1855 1856 i2c_del_adapter(&i2c_dev->adapter); 1857 pm_runtime_force_suspend(i2c_dev->dev); 1858 1859 tegra_i2c_release_dma(i2c_dev); 1860 tegra_i2c_release_clocks(i2c_dev); 1861} 1862 1863static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 1864{ 1865 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1866 int err; 1867 1868 err = pinctrl_pm_select_default_state(dev); 1869 if (err) 1870 return err; 1871 1872 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); 1873 if (err) 1874 return err; 1875 1876 /* 1877 * VI I2C device is attached to VE power domain which goes through 1878 * power ON/OFF during runtime PM resume/suspend, meaning that 1879 * controller needs to be re-initialized after power ON. 1880 */ 1881 if (IS_VI(i2c_dev)) { 1882 err = tegra_i2c_init(i2c_dev); 1883 if (err) 1884 goto disable_clocks; 1885 } 1886 1887 return 0; 1888 1889disable_clocks: 1890 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1891 1892 return err; 1893} 1894 1895static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 1896{ 1897 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1898 1899 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); 1900 1901 return pinctrl_pm_select_idle_state(dev); 1902} 1903 1904static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1905{ 1906 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1907 int err; 1908 1909 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1910 1911 if (!pm_runtime_status_suspended(dev)) { 1912 err = tegra_i2c_runtime_suspend(dev); 1913 if (err) 1914 return err; 1915 } 1916 1917 return 0; 1918} 1919 1920static int __maybe_unused tegra_i2c_resume(struct device *dev) 1921{ 1922 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1923 int err; 1924 1925 /* 1926 * We need to ensure that clocks are enabled so that registers can be 1927 * restored in tegra_i2c_init(). 1928 */ 1929 err = tegra_i2c_runtime_resume(dev); 1930 if (err) 1931 return err; 1932 1933 err = tegra_i2c_init(i2c_dev); 1934 if (err) 1935 return err; 1936 1937 /* 1938 * In case we are runtime suspended, disable clocks again so that we 1939 * don't unbalance the clock reference counts during the next runtime 1940 * resume transition. 1941 */ 1942 if (pm_runtime_status_suspended(dev)) { 1943 err = tegra_i2c_runtime_suspend(dev); 1944 if (err) 1945 return err; 1946 } 1947 1948 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1949 1950 return 0; 1951} 1952 1953static const struct dev_pm_ops tegra_i2c_pm = { 1954 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1955 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1956 NULL) 1957}; 1958 1959static const struct acpi_device_id tegra_i2c_acpi_match[] = { 1960 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw}, 1961 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw}, 1962 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw}, 1963 { } 1964}; 1965MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); 1966 1967static struct platform_driver tegra_i2c_driver = { 1968 .probe = tegra_i2c_probe, 1969 .remove_new = tegra_i2c_remove, 1970 .driver = { 1971 .name = "tegra-i2c", 1972 .of_match_table = tegra_i2c_of_match, 1973 .acpi_match_table = tegra_i2c_acpi_match, 1974 .pm = &tegra_i2c_pm, 1975 }, 1976}; 1977module_platform_driver(tegra_i2c_driver); 1978 1979MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver"); 1980MODULE_AUTHOR("Colin Cross"); 1981MODULE_LICENSE("GPL v2"); 1982