1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Core SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14#include <linux/bitfield.h> 15#include <linux/debugfs.h> 16#include <linux/delay.h> 17#include <linux/dmi.h> 18#include <linux/io.h> 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/slab.h> 22#include <linux/suspend.h> 23#include <linux/units.h> 24 25#include <asm/cpu_device_id.h> 26#include <asm/intel-family.h> 27#include <asm/msr.h> 28#include <asm/tsc.h> 29 30#include "core.h" 31#include "../pmt/telemetry.h" 32 33/* Maximum number of modes supported by platfoms that has low power mode capability */ 34const char *pmc_lpm_modes[] = { 35 "S0i2.0", 36 "S0i2.1", 37 "S0i2.2", 38 "S0i3.0", 39 "S0i3.1", 40 "S0i3.2", 41 "S0i3.3", 42 "S0i3.4", 43 NULL 44}; 45 46/* PKGC MSRs are common across Intel Core SoCs */ 47const struct pmc_bit_map msr_map[] = { 48 {"Package C2", MSR_PKG_C2_RESIDENCY}, 49 {"Package C3", MSR_PKG_C3_RESIDENCY}, 50 {"Package C6", MSR_PKG_C6_RESIDENCY}, 51 {"Package C7", MSR_PKG_C7_RESIDENCY}, 52 {"Package C8", MSR_PKG_C8_RESIDENCY}, 53 {"Package C9", MSR_PKG_C9_RESIDENCY}, 54 {"Package C10", MSR_PKG_C10_RESIDENCY}, 55 {} 56}; 57 58static inline u32 pmc_core_reg_read(struct pmc *pmc, int reg_offset) 59{ 60 return readl(pmc->regbase + reg_offset); 61} 62 63static inline void pmc_core_reg_write(struct pmc *pmc, int reg_offset, 64 u32 val) 65{ 66 writel(val, pmc->regbase + reg_offset); 67} 68 69static inline u64 pmc_core_adjust_slp_s0_step(struct pmc *pmc, u32 value) 70{ 71 /* 72 * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are 73 * used as a workaround which uses 30.5 usec tick. All other client 74 * programs have the legacy SLP_S0 residency counter that is using the 122 75 * usec tick. 76 */ 77 const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2; 78 79 if (pmc->map == &adl_reg_map) 80 return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2); 81 else 82 return (u64)value * pmc->map->slp_s0_res_counter_step; 83} 84 85static int set_etr3(struct pmc_dev *pmcdev) 86{ 87 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 88 const struct pmc_reg_map *map = pmc->map; 89 u32 reg; 90 int err; 91 92 if (!map->etr3_offset) 93 return -EOPNOTSUPP; 94 95 mutex_lock(&pmcdev->lock); 96 97 /* check if CF9 is locked */ 98 reg = pmc_core_reg_read(pmc, map->etr3_offset); 99 if (reg & ETR3_CF9LOCK) { 100 err = -EACCES; 101 goto out_unlock; 102 } 103 104 /* write CF9 global reset bit */ 105 reg |= ETR3_CF9GR; 106 pmc_core_reg_write(pmc, map->etr3_offset, reg); 107 108 reg = pmc_core_reg_read(pmc, map->etr3_offset); 109 if (!(reg & ETR3_CF9GR)) { 110 err = -EIO; 111 goto out_unlock; 112 } 113 114 err = 0; 115 116out_unlock: 117 mutex_unlock(&pmcdev->lock); 118 return err; 119} 120static umode_t etr3_is_visible(struct kobject *kobj, 121 struct attribute *attr, 122 int idx) 123{ 124 struct device *dev = kobj_to_dev(kobj); 125 struct pmc_dev *pmcdev = dev_get_drvdata(dev); 126 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 127 const struct pmc_reg_map *map = pmc->map; 128 u32 reg; 129 130 mutex_lock(&pmcdev->lock); 131 reg = pmc_core_reg_read(pmc, map->etr3_offset); 132 mutex_unlock(&pmcdev->lock); 133 134 return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->mode; 135} 136 137static ssize_t etr3_show(struct device *dev, 138 struct device_attribute *attr, char *buf) 139{ 140 struct pmc_dev *pmcdev = dev_get_drvdata(dev); 141 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 142 const struct pmc_reg_map *map = pmc->map; 143 u32 reg; 144 145 if (!map->etr3_offset) 146 return -EOPNOTSUPP; 147 148 mutex_lock(&pmcdev->lock); 149 150 reg = pmc_core_reg_read(pmc, map->etr3_offset); 151 reg &= ETR3_CF9GR | ETR3_CF9LOCK; 152 153 mutex_unlock(&pmcdev->lock); 154 155 return sysfs_emit(buf, "0x%08x", reg); 156} 157 158static ssize_t etr3_store(struct device *dev, 159 struct device_attribute *attr, 160 const char *buf, size_t len) 161{ 162 struct pmc_dev *pmcdev = dev_get_drvdata(dev); 163 int err; 164 u32 reg; 165 166 err = kstrtouint(buf, 16, ®); 167 if (err) 168 return err; 169 170 /* allow only CF9 writes */ 171 if (reg != ETR3_CF9GR) 172 return -EINVAL; 173 174 err = set_etr3(pmcdev); 175 if (err) 176 return err; 177 178 return len; 179} 180static DEVICE_ATTR_RW(etr3); 181 182static struct attribute *pmc_attrs[] = { 183 &dev_attr_etr3.attr, 184 NULL 185}; 186 187static const struct attribute_group pmc_attr_group = { 188 .attrs = pmc_attrs, 189 .is_visible = etr3_is_visible, 190}; 191 192static const struct attribute_group *pmc_dev_groups[] = { 193 &pmc_attr_group, 194 NULL 195}; 196 197static int pmc_core_dev_state_get(void *data, u64 *val) 198{ 199 struct pmc *pmc = data; 200 const struct pmc_reg_map *map = pmc->map; 201 u32 value; 202 203 value = pmc_core_reg_read(pmc, map->slp_s0_offset); 204 *val = pmc_core_adjust_slp_s0_step(pmc, value); 205 206 return 0; 207} 208 209DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n"); 210 211static int pmc_core_pson_residency_get(void *data, u64 *val) 212{ 213 struct pmc *pmc = data; 214 const struct pmc_reg_map *map = pmc->map; 215 u32 value; 216 217 value = pmc_core_reg_read(pmc, map->pson_residency_offset); 218 *val = (u64)value * map->pson_residency_counter_step; 219 220 return 0; 221} 222 223DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_pson_residency, pmc_core_pson_residency_get, NULL, "%llu\n"); 224 225static int pmc_core_check_read_lock_bit(struct pmc *pmc) 226{ 227 u32 value; 228 229 value = pmc_core_reg_read(pmc, pmc->map->pm_cfg_offset); 230 return value & BIT(pmc->map->pm_read_disable_bit); 231} 232 233static void pmc_core_slps0_display(struct pmc *pmc, struct device *dev, 234 struct seq_file *s) 235{ 236 const struct pmc_bit_map **maps = pmc->map->slps0_dbg_maps; 237 const struct pmc_bit_map *map; 238 int offset = pmc->map->slps0_dbg_offset; 239 u32 data; 240 241 while (*maps) { 242 map = *maps; 243 data = pmc_core_reg_read(pmc, offset); 244 offset += 4; 245 while (map->name) { 246 if (dev) 247 dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n", 248 map->name, 249 data & map->bit_mask ? "Yes" : "No"); 250 if (s) 251 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n", 252 map->name, 253 data & map->bit_mask ? "Yes" : "No"); 254 ++map; 255 } 256 ++maps; 257 } 258} 259 260static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps) 261{ 262 int idx; 263 264 for (idx = 0; maps[idx]; idx++) 265 ;/* Nothing */ 266 267 return idx; 268} 269 270static void pmc_core_lpm_display(struct pmc *pmc, struct device *dev, 271 struct seq_file *s, u32 offset, int pmc_index, 272 const char *str, 273 const struct pmc_bit_map **maps) 274{ 275 int index, idx, len = 32, bit_mask, arr_size; 276 u32 *lpm_regs; 277 278 arr_size = pmc_core_lpm_get_arr_size(maps); 279 lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL); 280 if (!lpm_regs) 281 return; 282 283 for (index = 0; index < arr_size; index++) { 284 lpm_regs[index] = pmc_core_reg_read(pmc, offset); 285 offset += 4; 286 } 287 288 for (idx = 0; idx < arr_size; idx++) { 289 if (dev) 290 dev_info(dev, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx, 291 lpm_regs[idx]); 292 if (s) 293 seq_printf(s, "\nPMC%d:LPM_%s_%d:\t0x%x\n", pmc_index, str, idx, 294 lpm_regs[idx]); 295 for (index = 0; maps[idx][index].name && index < len; index++) { 296 bit_mask = maps[idx][index].bit_mask; 297 if (dev) 298 dev_info(dev, "PMC%d:%-30s %-30d\n", pmc_index, 299 maps[idx][index].name, 300 lpm_regs[idx] & bit_mask ? 1 : 0); 301 if (s) 302 seq_printf(s, "PMC%d:%-30s %-30d\n", pmc_index, 303 maps[idx][index].name, 304 lpm_regs[idx] & bit_mask ? 1 : 0); 305 } 306 } 307 308 kfree(lpm_regs); 309} 310 311static bool slps0_dbg_latch; 312 313static inline u8 pmc_core_reg_read_byte(struct pmc *pmc, int offset) 314{ 315 return readb(pmc->regbase + offset); 316} 317 318static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip, 319 int pmc_index, u8 pf_reg, const struct pmc_bit_map **pf_map) 320{ 321 seq_printf(s, "PMC%d:PCH IP: %-2d - %-32s\tState: %s\n", 322 pmc_index, ip, pf_map[idx][index].name, 323 pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On"); 324} 325 326static int pmc_core_ppfear_show(struct seq_file *s, void *unused) 327{ 328 struct pmc_dev *pmcdev = s->private; 329 int i; 330 331 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 332 struct pmc *pmc = pmcdev->pmcs[i]; 333 const struct pmc_bit_map **maps; 334 u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES]; 335 int index, iter, idx, ip = 0; 336 337 if (!pmc) 338 continue; 339 340 maps = pmc->map->pfear_sts; 341 iter = pmc->map->ppfear0_offset; 342 343 for (index = 0; index < pmc->map->ppfear_buckets && 344 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) 345 pf_regs[index] = pmc_core_reg_read_byte(pmc, iter); 346 347 for (idx = 0; maps[idx]; idx++) { 348 for (index = 0; maps[idx][index].name && 349 index < pmc->map->ppfear_buckets * 8; ip++, index++) 350 pmc_core_display_map(s, index, idx, ip, i, 351 pf_regs[index / 8], maps); 352 } 353 } 354 355 return 0; 356} 357DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear); 358 359/* This function should return link status, 0 means ready */ 360static int pmc_core_mtpmc_link_status(struct pmc *pmc) 361{ 362 u32 value; 363 364 value = pmc_core_reg_read(pmc, SPT_PMC_PM_STS_OFFSET); 365 return value & BIT(SPT_PMC_MSG_FULL_STS_BIT); 366} 367 368static int pmc_core_send_msg(struct pmc *pmc, u32 *addr_xram) 369{ 370 u32 dest; 371 int timeout; 372 373 for (timeout = NUM_RETRIES; timeout > 0; timeout--) { 374 if (pmc_core_mtpmc_link_status(pmc) == 0) 375 break; 376 msleep(5); 377 } 378 379 if (timeout <= 0 && pmc_core_mtpmc_link_status(pmc)) 380 return -EBUSY; 381 382 dest = (*addr_xram & MTPMC_MASK) | (1U << 1); 383 pmc_core_reg_write(pmc, SPT_PMC_MTPMC_OFFSET, dest); 384 return 0; 385} 386 387static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused) 388{ 389 struct pmc_dev *pmcdev = s->private; 390 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 391 const struct pmc_bit_map *map = pmc->map->mphy_sts; 392 u32 mphy_core_reg_low, mphy_core_reg_high; 393 u32 val_low, val_high; 394 int index, err = 0; 395 396 if (pmcdev->pmc_xram_read_bit) { 397 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS."); 398 return 0; 399 } 400 401 mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16); 402 mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16); 403 404 mutex_lock(&pmcdev->lock); 405 406 if (pmc_core_send_msg(pmc, &mphy_core_reg_low) != 0) { 407 err = -EBUSY; 408 goto out_unlock; 409 } 410 411 msleep(10); 412 val_low = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); 413 414 if (pmc_core_send_msg(pmc, &mphy_core_reg_high) != 0) { 415 err = -EBUSY; 416 goto out_unlock; 417 } 418 419 msleep(10); 420 val_high = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); 421 422 for (index = 0; index < 8 && map[index].name; index++) { 423 seq_printf(s, "%-32s\tState: %s\n", 424 map[index].name, 425 map[index].bit_mask & val_low ? "Not power gated" : 426 "Power gated"); 427 } 428 429 for (index = 8; map[index].name; index++) { 430 seq_printf(s, "%-32s\tState: %s\n", 431 map[index].name, 432 map[index].bit_mask & val_high ? "Not power gated" : 433 "Power gated"); 434 } 435 436out_unlock: 437 mutex_unlock(&pmcdev->lock); 438 return err; 439} 440DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg); 441 442static int pmc_core_pll_show(struct seq_file *s, void *unused) 443{ 444 struct pmc_dev *pmcdev = s->private; 445 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 446 const struct pmc_bit_map *map = pmc->map->pll_sts; 447 u32 mphy_common_reg, val; 448 int index, err = 0; 449 450 if (pmcdev->pmc_xram_read_bit) { 451 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS."); 452 return 0; 453 } 454 455 mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16); 456 mutex_lock(&pmcdev->lock); 457 458 if (pmc_core_send_msg(pmc, &mphy_common_reg) != 0) { 459 err = -EBUSY; 460 goto out_unlock; 461 } 462 463 /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */ 464 msleep(10); 465 val = pmc_core_reg_read(pmc, SPT_PMC_MFPMC_OFFSET); 466 467 for (index = 0; map[index].name ; index++) { 468 seq_printf(s, "%-32s\tState: %s\n", 469 map[index].name, 470 map[index].bit_mask & val ? "Active" : "Idle"); 471 } 472 473out_unlock: 474 mutex_unlock(&pmcdev->lock); 475 return err; 476} 477DEFINE_SHOW_ATTRIBUTE(pmc_core_pll); 478 479int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore) 480{ 481 struct pmc *pmc; 482 const struct pmc_reg_map *map; 483 u32 reg; 484 int pmc_index, ltr_index; 485 486 ltr_index = value; 487 /* For platforms with multiple pmcs, ltr index value given by user 488 * is based on the contiguous indexes from ltr_show output. 489 * pmc index and ltr index needs to be calculated from it. 490 */ 491 for (pmc_index = 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs) && ltr_index >= 0; pmc_index++) { 492 pmc = pmcdev->pmcs[pmc_index]; 493 494 if (!pmc) 495 continue; 496 497 map = pmc->map; 498 if (ltr_index <= map->ltr_ignore_max) 499 break; 500 501 /* Along with IP names, ltr_show map includes CURRENT_PLATFORM 502 * and AGGREGATED_SYSTEM values per PMC. Take these two index 503 * values into account in ltr_index calculation. Also, to start 504 * ltr index from zero for next pmc, subtract it by 1. 505 */ 506 ltr_index = ltr_index - (map->ltr_ignore_max + 2) - 1; 507 } 508 509 if (pmc_index >= ARRAY_SIZE(pmcdev->pmcs) || ltr_index < 0) 510 return -EINVAL; 511 512 pr_debug("ltr_ignore for pmc%d: ltr_index:%d\n", pmc_index, ltr_index); 513 514 mutex_lock(&pmcdev->lock); 515 516 reg = pmc_core_reg_read(pmc, map->ltr_ignore_offset); 517 if (ignore) 518 reg |= BIT(ltr_index); 519 else 520 reg &= ~BIT(ltr_index); 521 pmc_core_reg_write(pmc, map->ltr_ignore_offset, reg); 522 523 mutex_unlock(&pmcdev->lock); 524 525 return 0; 526} 527 528static ssize_t pmc_core_ltr_ignore_write(struct file *file, 529 const char __user *userbuf, 530 size_t count, loff_t *ppos) 531{ 532 struct seq_file *s = file->private_data; 533 struct pmc_dev *pmcdev = s->private; 534 u32 buf_size, value; 535 int err; 536 537 buf_size = min_t(u32, count, 64); 538 539 err = kstrtou32_from_user(userbuf, buf_size, 10, &value); 540 if (err) 541 return err; 542 543 err = pmc_core_send_ltr_ignore(pmcdev, value, 1); 544 545 return err == 0 ? count : err; 546} 547 548static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused) 549{ 550 return 0; 551} 552 553static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file) 554{ 555 return single_open(file, pmc_core_ltr_ignore_show, inode->i_private); 556} 557 558static const struct file_operations pmc_core_ltr_ignore_ops = { 559 .open = pmc_core_ltr_ignore_open, 560 .read = seq_read, 561 .write = pmc_core_ltr_ignore_write, 562 .llseek = seq_lseek, 563 .release = single_release, 564}; 565 566static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset) 567{ 568 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 569 const struct pmc_reg_map *map = pmc->map; 570 u32 fd; 571 572 mutex_lock(&pmcdev->lock); 573 574 if (!reset && !slps0_dbg_latch) 575 goto out_unlock; 576 577 fd = pmc_core_reg_read(pmc, map->slps0_dbg_offset); 578 if (reset) 579 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS; 580 else 581 fd |= CNP_PMC_LATCH_SLPS0_EVENTS; 582 pmc_core_reg_write(pmc, map->slps0_dbg_offset, fd); 583 584 slps0_dbg_latch = false; 585 586out_unlock: 587 mutex_unlock(&pmcdev->lock); 588} 589 590static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused) 591{ 592 struct pmc_dev *pmcdev = s->private; 593 594 pmc_core_slps0_dbg_latch(pmcdev, false); 595 pmc_core_slps0_display(pmcdev->pmcs[PMC_IDX_MAIN], NULL, s); 596 pmc_core_slps0_dbg_latch(pmcdev, true); 597 598 return 0; 599} 600DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg); 601 602static u32 convert_ltr_scale(u32 val) 603{ 604 /* 605 * As per PCIE specification supporting document 606 * ECN_LatencyTolnReporting_14Aug08.pdf the Latency 607 * Tolerance Reporting data payload is encoded in a 608 * 3 bit scale and 10 bit value fields. Values are 609 * multiplied by the indicated scale to yield an absolute time 610 * value, expressible in a range from 1 nanosecond to 611 * 2^25*(2^10-1) = 34,326,183,936 nanoseconds. 612 * 613 * scale encoding is as follows: 614 * 615 * ---------------------------------------------- 616 * |scale factor | Multiplier (ns) | 617 * ---------------------------------------------- 618 * | 0 | 1 | 619 * | 1 | 32 | 620 * | 2 | 1024 | 621 * | 3 | 32768 | 622 * | 4 | 1048576 | 623 * | 5 | 33554432 | 624 * | 6 | Invalid | 625 * | 7 | Invalid | 626 * ---------------------------------------------- 627 */ 628 if (val > 5) { 629 pr_warn("Invalid LTR scale factor.\n"); 630 return 0; 631 } 632 633 return 1U << (5 * val); 634} 635 636static int pmc_core_ltr_show(struct seq_file *s, void *unused) 637{ 638 struct pmc_dev *pmcdev = s->private; 639 u64 decoded_snoop_ltr, decoded_non_snoop_ltr; 640 u32 ltr_raw_data, scale, val; 641 u16 snoop_ltr, nonsnoop_ltr; 642 int i, index, ltr_index = 0; 643 644 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 645 struct pmc *pmc = pmcdev->pmcs[i]; 646 const struct pmc_bit_map *map; 647 648 if (!pmc) 649 continue; 650 651 map = pmc->map->ltr_show_sts; 652 for (index = 0; map[index].name; index++) { 653 decoded_snoop_ltr = decoded_non_snoop_ltr = 0; 654 ltr_raw_data = pmc_core_reg_read(pmc, 655 map[index].bit_mask); 656 snoop_ltr = ltr_raw_data & ~MTPMC_MASK; 657 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK; 658 659 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) { 660 scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr); 661 val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr); 662 decoded_non_snoop_ltr = val * convert_ltr_scale(scale); 663 } 664 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) { 665 scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr); 666 val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr); 667 decoded_snoop_ltr = val * convert_ltr_scale(scale); 668 } 669 670 seq_printf(s, "%d\tPMC%d:%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n", 671 ltr_index, i, map[index].name, ltr_raw_data, 672 decoded_non_snoop_ltr, 673 decoded_snoop_ltr); 674 ltr_index++; 675 } 676 } 677 return 0; 678} 679DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); 680 681static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset, 682 const int lpm_adj_x2) 683{ 684 u64 lpm_res = pmc_core_reg_read(pmc, offset); 685 686 return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res); 687} 688 689static int pmc_core_substate_res_show(struct seq_file *s, void *unused) 690{ 691 struct pmc_dev *pmcdev = s->private; 692 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 693 const int lpm_adj_x2 = pmc->map->lpm_res_counter_step_x2; 694 u32 offset = pmc->map->lpm_residency_offset; 695 int i, mode; 696 697 seq_printf(s, "%-10s %-15s\n", "Substate", "Residency"); 698 699 pmc_for_each_mode(i, mode, pmcdev) { 700 seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode], 701 adjust_lpm_residency(pmc, offset + (4 * mode), lpm_adj_x2)); 702 } 703 704 return 0; 705} 706DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); 707 708static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) 709{ 710 struct pmc_dev *pmcdev = s->private; 711 int i; 712 713 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 714 struct pmc *pmc = pmcdev->pmcs[i]; 715 const struct pmc_bit_map **maps; 716 u32 offset; 717 718 if (!pmc) 719 continue; 720 maps = pmc->map->lpm_sts; 721 offset = pmc->map->lpm_status_offset; 722 pmc_core_lpm_display(pmc, NULL, s, offset, i, "STATUS", maps); 723 } 724 725 return 0; 726} 727DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); 728 729static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused) 730{ 731 struct pmc_dev *pmcdev = s->private; 732 int i; 733 734 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 735 struct pmc *pmc = pmcdev->pmcs[i]; 736 const struct pmc_bit_map **maps; 737 u32 offset; 738 739 if (!pmc) 740 continue; 741 maps = pmc->map->lpm_sts; 742 offset = pmc->map->lpm_live_status_offset; 743 pmc_core_lpm_display(pmc, NULL, s, offset, i, "LIVE_STATUS", maps); 744 } 745 746 return 0; 747} 748DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); 749 750static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_index) 751{ 752 struct pmc_dev *pmcdev = s->private; 753 int i, mode; 754 755 seq_printf(s, "%30s |", "Element"); 756 pmc_for_each_mode(i, mode, pmcdev) 757 seq_printf(s, " %9s |", pmc_lpm_modes[mode]); 758 759 seq_printf(s, " %9s |\n", "Status"); 760} 761 762static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) 763{ 764 struct pmc_dev *pmcdev = s->private; 765 u32 sts_offset; 766 u32 *lpm_req_regs; 767 int num_maps, mp, pmc_index; 768 769 for (pmc_index = 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs); ++pmc_index) { 770 struct pmc *pmc = pmcdev->pmcs[pmc_index]; 771 const struct pmc_bit_map **maps; 772 773 if (!pmc) 774 continue; 775 776 maps = pmc->map->lpm_sts; 777 num_maps = pmc->map->lpm_num_maps; 778 sts_offset = pmc->map->lpm_status_offset; 779 lpm_req_regs = pmc->lpm_req_regs; 780 781 /* 782 * When there are multiple PMCs, though the PMC may exist, the 783 * requirement register discovery could have failed so check 784 * before accessing. 785 */ 786 if (!lpm_req_regs) 787 continue; 788 789 /* Display the header */ 790 pmc_core_substate_req_header_show(s, pmc_index); 791 792 /* Loop over maps */ 793 for (mp = 0; mp < num_maps; mp++) { 794 u32 req_mask = 0; 795 u32 lpm_status; 796 const struct pmc_bit_map *map; 797 int mode, idx, i, len = 32; 798 799 /* 800 * Capture the requirements and create a mask so that we only 801 * show an element if it's required for at least one of the 802 * enabled low power modes 803 */ 804 pmc_for_each_mode(idx, mode, pmcdev) 805 req_mask |= lpm_req_regs[mp + (mode * num_maps)]; 806 807 /* Get the last latched status for this map */ 808 lpm_status = pmc_core_reg_read(pmc, sts_offset + (mp * 4)); 809 810 /* Loop over elements in this map */ 811 map = maps[mp]; 812 for (i = 0; map[i].name && i < len; i++) { 813 u32 bit_mask = map[i].bit_mask; 814 815 if (!(bit_mask & req_mask)) { 816 /* 817 * Not required for any enabled states 818 * so don't display 819 */ 820 continue; 821 } 822 823 /* Display the element name in the first column */ 824 seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name); 825 826 /* Loop over the enabled states and display if required */ 827 pmc_for_each_mode(idx, mode, pmcdev) { 828 bool required = lpm_req_regs[mp + (mode * num_maps)] & 829 bit_mask; 830 seq_printf(s, " %9s |", required ? "Required" : " "); 831 } 832 833 /* In Status column, show the last captured state of this agent */ 834 seq_printf(s, " %9s |", lpm_status & bit_mask ? "Yes" : " "); 835 836 seq_puts(s, "\n"); 837 } 838 } 839 } 840 return 0; 841} 842DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); 843 844static unsigned int pmc_core_get_crystal_freq(void) 845{ 846 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; 847 848 if (boot_cpu_data.cpuid_level < 0x15) 849 return 0; 850 851 eax_denominator = ebx_numerator = ecx_hz = edx = 0; 852 853 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ 854 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); 855 856 if (ebx_numerator == 0 || eax_denominator == 0) 857 return 0; 858 859 return ecx_hz; 860} 861 862static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused) 863{ 864 struct pmc_dev *pmcdev = s->private; 865 u64 die_c6_res, count; 866 int ret; 867 868 if (!pmcdev->crystal_freq) { 869 dev_warn_once(&pmcdev->pdev->dev, "Crystal frequency unavailable\n"); 870 return -ENXIO; 871 } 872 873 ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset, 874 &count, 1); 875 if (ret) 876 return ret; 877 878 die_c6_res = div64_u64(count * HZ_PER_MHZ, pmcdev->crystal_freq); 879 seq_printf(s, "%llu\n", die_c6_res); 880 881 return 0; 882} 883DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us); 884 885static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused) 886{ 887 struct pmc_dev *pmcdev = s->private; 888 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 889 bool c10; 890 u32 reg; 891 int idx, mode; 892 893 reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset); 894 if (reg & LPM_STS_LATCH_MODE) { 895 seq_puts(s, "c10"); 896 c10 = false; 897 } else { 898 seq_puts(s, "[c10]"); 899 c10 = true; 900 } 901 902 pmc_for_each_mode(idx, mode, pmcdev) { 903 if ((BIT(mode) & reg) && !c10) 904 seq_printf(s, " [%s]", pmc_lpm_modes[mode]); 905 else 906 seq_printf(s, " %s", pmc_lpm_modes[mode]); 907 } 908 909 seq_puts(s, " clear\n"); 910 911 return 0; 912} 913 914static ssize_t pmc_core_lpm_latch_mode_write(struct file *file, 915 const char __user *userbuf, 916 size_t count, loff_t *ppos) 917{ 918 struct seq_file *s = file->private_data; 919 struct pmc_dev *pmcdev = s->private; 920 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 921 bool clear = false, c10 = false; 922 unsigned char buf[8]; 923 int idx, m, mode; 924 u32 reg; 925 926 if (count > sizeof(buf) - 1) 927 return -EINVAL; 928 if (copy_from_user(buf, userbuf, count)) 929 return -EFAULT; 930 buf[count] = '\0'; 931 932 /* 933 * Allowed strings are: 934 * Any enabled substate, e.g. 'S0i2.0' 935 * 'c10' 936 * 'clear' 937 */ 938 mode = sysfs_match_string(pmc_lpm_modes, buf); 939 940 /* Check string matches enabled mode */ 941 pmc_for_each_mode(idx, m, pmcdev) 942 if (mode == m) 943 break; 944 945 if (mode != m || mode < 0) { 946 if (sysfs_streq(buf, "clear")) 947 clear = true; 948 else if (sysfs_streq(buf, "c10")) 949 c10 = true; 950 else 951 return -EINVAL; 952 } 953 954 if (clear) { 955 mutex_lock(&pmcdev->lock); 956 957 reg = pmc_core_reg_read(pmc, pmc->map->etr3_offset); 958 reg |= ETR3_CLEAR_LPM_EVENTS; 959 pmc_core_reg_write(pmc, pmc->map->etr3_offset, reg); 960 961 mutex_unlock(&pmcdev->lock); 962 963 return count; 964 } 965 966 if (c10) { 967 mutex_lock(&pmcdev->lock); 968 969 reg = pmc_core_reg_read(pmc, pmc->map->lpm_sts_latch_en_offset); 970 reg &= ~LPM_STS_LATCH_MODE; 971 pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg); 972 973 mutex_unlock(&pmcdev->lock); 974 975 return count; 976 } 977 978 /* 979 * For LPM mode latching we set the latch enable bit and selected mode 980 * and clear everything else. 981 */ 982 reg = LPM_STS_LATCH_MODE | BIT(mode); 983 mutex_lock(&pmcdev->lock); 984 pmc_core_reg_write(pmc, pmc->map->lpm_sts_latch_en_offset, reg); 985 mutex_unlock(&pmcdev->lock); 986 987 return count; 988} 989DEFINE_PMC_CORE_ATTR_WRITE(pmc_core_lpm_latch_mode); 990 991static int pmc_core_pkgc_show(struct seq_file *s, void *unused) 992{ 993 struct pmc *pmc = s->private; 994 const struct pmc_bit_map *map = pmc->map->msr_sts; 995 u64 pcstate_count; 996 int index; 997 998 for (index = 0; map[index].name ; index++) { 999 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count)) 1000 continue; 1001 1002 pcstate_count *= 1000; 1003 do_div(pcstate_count, tsc_khz); 1004 seq_printf(s, "%-8s : %llu\n", map[index].name, 1005 pcstate_count); 1006 } 1007 1008 return 0; 1009} 1010DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc); 1011 1012static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_order) 1013{ 1014 int i, j; 1015 1016 if (!lpm_pri) 1017 return false; 1018 /* 1019 * Each byte contains the priority level for 2 modes (7:4 and 3:0). 1020 * In a 32 bit register this allows for describing 8 modes. Store the 1021 * levels and look for values out of range. 1022 */ 1023 for (i = 0; i < 8; i++) { 1024 int level = lpm_pri & GENMASK(3, 0); 1025 1026 if (level >= LPM_MAX_NUM_MODES) 1027 return false; 1028 1029 mode_order[i] = level; 1030 lpm_pri >>= 4; 1031 } 1032 1033 /* Check that we have unique values */ 1034 for (i = 0; i < LPM_MAX_NUM_MODES - 1; i++) 1035 for (j = i + 1; j < LPM_MAX_NUM_MODES; j++) 1036 if (mode_order[i] == mode_order[j]) 1037 return false; 1038 1039 return true; 1040} 1041 1042void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev) 1043{ 1044 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 1045 u8 pri_order[LPM_MAX_NUM_MODES] = LPM_DEFAULT_PRI; 1046 u8 mode_order[LPM_MAX_NUM_MODES]; 1047 u32 lpm_pri; 1048 u32 lpm_en; 1049 int mode, i, p; 1050 1051 /* Use LPM Maps to indicate support for substates */ 1052 if (!pmc->map->lpm_num_maps) 1053 return; 1054 1055 lpm_en = pmc_core_reg_read(pmc, pmc->map->lpm_en_offset); 1056 /* For MTL, BIT 31 is not an lpm mode but a enable bit. 1057 * Lower byte is enough to cover the number of lpm modes for all 1058 * platforms and hence mask the upper 3 bytes. 1059 */ 1060 pmcdev->num_lpm_modes = hweight32(lpm_en & 0xFF); 1061 1062 /* Read 32 bit LPM_PRI register */ 1063 lpm_pri = pmc_core_reg_read(pmc, pmc->map->lpm_priority_offset); 1064 1065 1066 /* 1067 * If lpm_pri value passes verification, then override the default 1068 * modes here. Otherwise stick with the default. 1069 */ 1070 if (pmc_core_pri_verify(lpm_pri, mode_order)) 1071 /* Get list of modes in priority order */ 1072 for (mode = 0; mode < LPM_MAX_NUM_MODES; mode++) 1073 pri_order[mode_order[mode]] = mode; 1074 else 1075 dev_warn(&pmcdev->pdev->dev, 1076 "Assuming a default substate order for this platform\n"); 1077 1078 /* 1079 * Loop through all modes from lowest to highest priority, 1080 * and capture all enabled modes in order 1081 */ 1082 i = 0; 1083 for (p = LPM_MAX_NUM_MODES - 1; p >= 0; p--) { 1084 int mode = pri_order[p]; 1085 1086 if (!(BIT(mode) & lpm_en)) 1087 continue; 1088 1089 pmcdev->lpm_en_modes[i++] = mode; 1090 } 1091} 1092 1093int get_primary_reg_base(struct pmc *pmc) 1094{ 1095 u64 slp_s0_addr; 1096 1097 if (lpit_read_residency_count_address(&slp_s0_addr)) { 1098 pmc->base_addr = PMC_BASE_ADDR_DEFAULT; 1099 1100 if (page_is_ram(PHYS_PFN(pmc->base_addr))) 1101 return -ENODEV; 1102 } else { 1103 pmc->base_addr = slp_s0_addr - pmc->map->slp_s0_offset; 1104 } 1105 1106 pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length); 1107 if (!pmc->regbase) 1108 return -ENOMEM; 1109 return 0; 1110} 1111 1112void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid) 1113{ 1114 struct telem_endpoint *ep; 1115 struct pci_dev *pcidev; 1116 1117 pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(10, 0)); 1118 if (!pcidev) { 1119 dev_err(&pmcdev->pdev->dev, "PUNIT PMT device not found."); 1120 return; 1121 } 1122 1123 ep = pmt_telem_find_and_register_endpoint(pcidev, guid, 0); 1124 pci_dev_put(pcidev); 1125 if (IS_ERR(ep)) { 1126 dev_err(&pmcdev->pdev->dev, 1127 "pmc_core: couldn't get DMU telem endpoint %ld", 1128 PTR_ERR(ep)); 1129 return; 1130 } 1131 1132 pmcdev->punit_ep = ep; 1133 1134 pmcdev->has_die_c6 = true; 1135 pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET; 1136} 1137 1138void pmc_core_set_device_d3(unsigned int device) 1139{ 1140 struct pci_dev *pcidev; 1141 1142 pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1143 if (pcidev) { 1144 if (!device_trylock(&pcidev->dev)) { 1145 pci_dev_put(pcidev); 1146 return; 1147 } 1148 if (!pcidev->dev.driver) { 1149 dev_info(&pcidev->dev, "Setting to D3hot\n"); 1150 pci_set_power_state(pcidev, PCI_D3hot); 1151 } 1152 device_unlock(&pcidev->dev); 1153 pci_dev_put(pcidev); 1154 } 1155} 1156 1157static bool pmc_core_is_pson_residency_enabled(struct pmc_dev *pmcdev) 1158{ 1159 struct platform_device *pdev = pmcdev->pdev; 1160 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); 1161 u8 val; 1162 1163 if (!adev) 1164 return false; 1165 1166 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), 1167 "intel-cec-pson-switching-enabled-in-s0", 1168 &val)) 1169 return false; 1170 1171 return val == 1; 1172} 1173 1174 1175static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) 1176{ 1177 debugfs_remove_recursive(pmcdev->dbgfs_dir); 1178} 1179 1180static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) 1181{ 1182 struct pmc *primary_pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 1183 struct dentry *dir; 1184 1185 dir = debugfs_create_dir("pmc_core", NULL); 1186 pmcdev->dbgfs_dir = dir; 1187 1188 debugfs_create_file("slp_s0_residency_usec", 0444, dir, primary_pmc, 1189 &pmc_core_dev_state); 1190 1191 if (primary_pmc->map->pfear_sts) 1192 debugfs_create_file("pch_ip_power_gating_status", 0444, dir, 1193 pmcdev, &pmc_core_ppfear_fops); 1194 1195 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, 1196 &pmc_core_ltr_ignore_ops); 1197 1198 debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops); 1199 1200 debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc, 1201 &pmc_core_pkgc_fops); 1202 1203 if (primary_pmc->map->pll_sts) 1204 debugfs_create_file("pll_status", 0444, dir, pmcdev, 1205 &pmc_core_pll_fops); 1206 1207 if (primary_pmc->map->mphy_sts) 1208 debugfs_create_file("mphy_core_lanes_power_gating_status", 1209 0444, dir, pmcdev, 1210 &pmc_core_mphy_pg_fops); 1211 1212 if (primary_pmc->map->slps0_dbg_maps) { 1213 debugfs_create_file("slp_s0_debug_status", 0444, 1214 dir, pmcdev, 1215 &pmc_core_slps0_dbg_fops); 1216 1217 debugfs_create_bool("slp_s0_dbg_latch", 0644, 1218 dir, &slps0_dbg_latch); 1219 } 1220 1221 if (primary_pmc->map->lpm_en_offset) { 1222 debugfs_create_file("substate_residencies", 0444, 1223 pmcdev->dbgfs_dir, pmcdev, 1224 &pmc_core_substate_res_fops); 1225 } 1226 1227 if (primary_pmc->map->lpm_status_offset) { 1228 debugfs_create_file("substate_status_registers", 0444, 1229 pmcdev->dbgfs_dir, pmcdev, 1230 &pmc_core_substate_sts_regs_fops); 1231 debugfs_create_file("substate_live_status_registers", 0444, 1232 pmcdev->dbgfs_dir, pmcdev, 1233 &pmc_core_substate_l_sts_regs_fops); 1234 debugfs_create_file("lpm_latch_mode", 0644, 1235 pmcdev->dbgfs_dir, pmcdev, 1236 &pmc_core_lpm_latch_mode_fops); 1237 } 1238 1239 if (primary_pmc->lpm_req_regs) { 1240 debugfs_create_file("substate_requirements", 0444, 1241 pmcdev->dbgfs_dir, pmcdev, 1242 &pmc_core_substate_req_regs_fops); 1243 } 1244 1245 if (primary_pmc->map->pson_residency_offset && pmc_core_is_pson_residency_enabled(pmcdev)) { 1246 debugfs_create_file("pson_residency_usec", 0444, 1247 pmcdev->dbgfs_dir, primary_pmc, &pmc_core_pson_residency); 1248 } 1249 1250 if (pmcdev->has_die_c6) { 1251 debugfs_create_file("die_c6_us_show", 0444, 1252 pmcdev->dbgfs_dir, pmcdev, 1253 &pmc_core_die_c6_us_fops); 1254 } 1255} 1256 1257static const struct x86_cpu_id intel_pmc_core_ids[] = { 1258 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, spt_core_init), 1259 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, spt_core_init), 1260 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, spt_core_init), 1261 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, spt_core_init), 1262 X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, cnp_core_init), 1263 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, icl_core_init), 1264 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, icl_core_init), 1265 X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, cnp_core_init), 1266 X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, cnp_core_init), 1267 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_l_core_init), 1268 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, tgl_core_init), 1269 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_l_core_init), 1270 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, icl_core_init), 1271 X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, tgl_core_init), 1272 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_l_core_init), 1273 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, tgl_l_core_init), 1274 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, adl_core_init), 1275 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_l_core_init), 1276 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, adl_core_init), 1277 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, adl_core_init), 1278 X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, mtl_core_init), 1279 X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, arl_core_init), 1280 X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, lnl_core_init), 1281 {} 1282}; 1283 1284MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids); 1285 1286static const struct pci_device_id pmc_pci_ids[] = { 1287 { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) }, 1288 { } 1289}; 1290 1291/* 1292 * This quirk can be used on those platforms where 1293 * the platform BIOS enforces 24Mhz crystal to shutdown 1294 * before PMC can assert SLP_S0#. 1295 */ 1296static bool xtal_ignore; 1297static int quirk_xtal_ignore(const struct dmi_system_id *id) 1298{ 1299 xtal_ignore = true; 1300 return 0; 1301} 1302 1303static void pmc_core_xtal_ignore(struct pmc *pmc) 1304{ 1305 u32 value; 1306 1307 value = pmc_core_reg_read(pmc, pmc->map->pm_vric1_offset); 1308 /* 24MHz Crystal Shutdown Qualification Disable */ 1309 value |= SPT_PMC_VRIC1_XTALSDQDIS; 1310 /* Low Voltage Mode Enable */ 1311 value &= ~SPT_PMC_VRIC1_SLPS0LVEN; 1312 pmc_core_reg_write(pmc, pmc->map->pm_vric1_offset, value); 1313} 1314 1315static const struct dmi_system_id pmc_core_dmi_table[] = { 1316 { 1317 .callback = quirk_xtal_ignore, 1318 .ident = "HP Elite x2 1013 G3", 1319 .matches = { 1320 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1321 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"), 1322 }, 1323 }, 1324 {} 1325}; 1326 1327static void pmc_core_do_dmi_quirks(struct pmc *pmc) 1328{ 1329 dmi_check_system(pmc_core_dmi_table); 1330 1331 if (xtal_ignore) 1332 pmc_core_xtal_ignore(pmc); 1333} 1334 1335static void pmc_core_clean_structure(struct platform_device *pdev) 1336{ 1337 struct pmc_dev *pmcdev = platform_get_drvdata(pdev); 1338 int i; 1339 1340 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 1341 struct pmc *pmc = pmcdev->pmcs[i]; 1342 1343 if (pmc) 1344 iounmap(pmc->regbase); 1345 } 1346 1347 if (pmcdev->ssram_pcidev) { 1348 pci_dev_put(pmcdev->ssram_pcidev); 1349 pci_disable_device(pmcdev->ssram_pcidev); 1350 } 1351 1352 if (pmcdev->punit_ep) 1353 pmt_telem_unregister_endpoint(pmcdev->punit_ep); 1354 1355 platform_set_drvdata(pdev, NULL); 1356 mutex_destroy(&pmcdev->lock); 1357} 1358 1359static int pmc_core_probe(struct platform_device *pdev) 1360{ 1361 static bool device_initialized; 1362 struct pmc_dev *pmcdev; 1363 const struct x86_cpu_id *cpu_id; 1364 int (*core_init)(struct pmc_dev *pmcdev); 1365 struct pmc *primary_pmc; 1366 int ret; 1367 1368 if (device_initialized) 1369 return -ENODEV; 1370 1371 pmcdev = devm_kzalloc(&pdev->dev, sizeof(*pmcdev), GFP_KERNEL); 1372 if (!pmcdev) 1373 return -ENOMEM; 1374 1375 pmcdev->crystal_freq = pmc_core_get_crystal_freq(); 1376 1377 platform_set_drvdata(pdev, pmcdev); 1378 pmcdev->pdev = pdev; 1379 1380 cpu_id = x86_match_cpu(intel_pmc_core_ids); 1381 if (!cpu_id) 1382 return -ENODEV; 1383 1384 core_init = (int (*)(struct pmc_dev *))cpu_id->driver_data; 1385 1386 /* Primary PMC */ 1387 primary_pmc = devm_kzalloc(&pdev->dev, sizeof(*primary_pmc), GFP_KERNEL); 1388 if (!primary_pmc) 1389 return -ENOMEM; 1390 pmcdev->pmcs[PMC_IDX_MAIN] = primary_pmc; 1391 1392 /* The last element in msr_map is empty */ 1393 pmcdev->num_of_pkgc = ARRAY_SIZE(msr_map) - 1; 1394 pmcdev->pkgc_res_cnt = devm_kcalloc(&pdev->dev, 1395 pmcdev->num_of_pkgc, 1396 sizeof(*pmcdev->pkgc_res_cnt), 1397 GFP_KERNEL); 1398 if (!pmcdev->pkgc_res_cnt) 1399 return -ENOMEM; 1400 1401 /* 1402 * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here 1403 * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap 1404 * in this case. 1405 */ 1406 if (core_init == spt_core_init && !pci_dev_present(pmc_pci_ids)) 1407 core_init = cnp_core_init; 1408 1409 mutex_init(&pmcdev->lock); 1410 ret = core_init(pmcdev); 1411 if (ret) { 1412 pmc_core_clean_structure(pdev); 1413 return ret; 1414 } 1415 1416 pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(primary_pmc); 1417 pmc_core_do_dmi_quirks(primary_pmc); 1418 1419 pmc_core_dbgfs_register(pmcdev); 1420 pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) * 1421 pmc_core_adjust_slp_s0_step(primary_pmc, 1)); 1422 1423 device_initialized = true; 1424 dev_info(&pdev->dev, " initialized\n"); 1425 1426 return 0; 1427} 1428 1429static void pmc_core_remove(struct platform_device *pdev) 1430{ 1431 struct pmc_dev *pmcdev = platform_get_drvdata(pdev); 1432 pmc_core_dbgfs_unregister(pmcdev); 1433 pmc_core_clean_structure(pdev); 1434} 1435 1436static bool warn_on_s0ix_failures; 1437module_param(warn_on_s0ix_failures, bool, 0644); 1438MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures"); 1439 1440static __maybe_unused int pmc_core_suspend(struct device *dev) 1441{ 1442 struct pmc_dev *pmcdev = dev_get_drvdata(dev); 1443 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 1444 unsigned int i; 1445 1446 if (pmcdev->suspend) 1447 pmcdev->suspend(pmcdev); 1448 1449 /* Check if the syspend will actually use S0ix */ 1450 if (pm_suspend_via_firmware()) 1451 return 0; 1452 1453 /* Save PKGC residency for checking later */ 1454 for (i = 0; i < pmcdev->num_of_pkgc; i++) { 1455 if (rdmsrl_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i])) 1456 return -EIO; 1457 } 1458 1459 /* Save S0ix residency for checking later */ 1460 if (pmc_core_dev_state_get(pmc, &pmcdev->s0ix_counter)) 1461 return -EIO; 1462 1463 return 0; 1464} 1465 1466static inline bool pmc_core_is_deepest_pkgc_failed(struct pmc_dev *pmcdev) 1467{ 1468 u32 deepest_pkgc_msr = msr_map[pmcdev->num_of_pkgc - 1].bit_mask; 1469 u64 deepest_pkgc_residency; 1470 1471 if (rdmsrl_safe(deepest_pkgc_msr, &deepest_pkgc_residency)) 1472 return false; 1473 1474 if (deepest_pkgc_residency == pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1]) 1475 return true; 1476 1477 return false; 1478} 1479 1480static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev) 1481{ 1482 u64 s0ix_counter; 1483 1484 if (pmc_core_dev_state_get(pmcdev->pmcs[PMC_IDX_MAIN], &s0ix_counter)) 1485 return false; 1486 1487 pm_report_hw_sleep_time((u32)(s0ix_counter - pmcdev->s0ix_counter)); 1488 1489 if (s0ix_counter == pmcdev->s0ix_counter) 1490 return true; 1491 1492 return false; 1493} 1494 1495int pmc_core_resume_common(struct pmc_dev *pmcdev) 1496{ 1497 struct device *dev = &pmcdev->pdev->dev; 1498 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 1499 const struct pmc_bit_map **maps = pmc->map->lpm_sts; 1500 int offset = pmc->map->lpm_status_offset; 1501 int i; 1502 1503 /* Check if the syspend used S0ix */ 1504 if (pm_suspend_via_firmware()) 1505 return 0; 1506 1507 if (!pmc_core_is_s0ix_failed(pmcdev)) 1508 return 0; 1509 1510 if (!warn_on_s0ix_failures) 1511 return 0; 1512 1513 if (pmc_core_is_deepest_pkgc_failed(pmcdev)) { 1514 /* S0ix failed because of deepest PKGC entry failure */ 1515 dev_info(dev, "CPU did not enter %s!!! (%s cnt=0x%llx)\n", 1516 msr_map[pmcdev->num_of_pkgc - 1].name, 1517 msr_map[pmcdev->num_of_pkgc - 1].name, 1518 pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1]); 1519 1520 for (i = 0; i < pmcdev->num_of_pkgc; i++) { 1521 u64 pc_cnt; 1522 1523 if (!rdmsrl_safe(msr_map[i].bit_mask, &pc_cnt)) { 1524 dev_info(dev, "Prev %s cnt = 0x%llx, Current %s cnt = 0x%llx\n", 1525 msr_map[i].name, pmcdev->pkgc_res_cnt[i], 1526 msr_map[i].name, pc_cnt); 1527 } 1528 } 1529 return 0; 1530 } 1531 1532 /* The real interesting case - S0ix failed - lets ask PMC why. */ 1533 dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n", 1534 pmcdev->s0ix_counter); 1535 1536 if (pmc->map->slps0_dbg_maps) 1537 pmc_core_slps0_display(pmc, dev, NULL); 1538 1539 for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { 1540 struct pmc *pmc = pmcdev->pmcs[i]; 1541 1542 if (!pmc) 1543 continue; 1544 if (pmc->map->lpm_sts) 1545 pmc_core_lpm_display(pmc, dev, NULL, offset, i, "STATUS", maps); 1546 } 1547 1548 return 0; 1549} 1550 1551static __maybe_unused int pmc_core_resume(struct device *dev) 1552{ 1553 struct pmc_dev *pmcdev = dev_get_drvdata(dev); 1554 1555 if (pmcdev->resume) 1556 return pmcdev->resume(pmcdev); 1557 1558 return pmc_core_resume_common(pmcdev); 1559} 1560 1561static const struct dev_pm_ops pmc_core_pm_ops = { 1562 SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume) 1563}; 1564 1565static const struct acpi_device_id pmc_core_acpi_ids[] = { 1566 {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/ 1567 { } 1568}; 1569MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids); 1570 1571static struct platform_driver pmc_core_driver = { 1572 .driver = { 1573 .name = "intel_pmc_core", 1574 .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids), 1575 .pm = &pmc_core_pm_ops, 1576 .dev_groups = pmc_dev_groups, 1577 }, 1578 .probe = pmc_core_probe, 1579 .remove_new = pmc_core_remove, 1580}; 1581 1582module_platform_driver(pmc_core_driver); 1583 1584MODULE_LICENSE("GPL v2"); 1585MODULE_DESCRIPTION("Intel PMC Core Driver"); 1586