#
4e8303cf |
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11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50fbe0cc |
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23-Jul-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Add -ENOMEM error handling when there is no memory Return -ENOMEM, when there is no sufficient dynamically allocated memory Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
93ab59ac |
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12-May-2023 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: switch to unified amdgpu_ring_test_helper This will simplify code. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e602157e |
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17-May-2023 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: fix S3 issue if MQD in VRAM 1. Need flush HDP for MQD putting in vram 2. Zero out mes MQD Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f4caf584 |
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14-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3) v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1cfb4d61 |
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26-Apr-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: put MQDs in VRAM Reduces preemption latency. Only enable this for gfx10 and 11 for now to avoid changing behavior on gfx 8 and 9. v2: move MES MQDs into VRAM as well (YuBiao) v3: enable on gfx10, 11 only (Alex) v4: minor style changes, document why gfx10/11 only (Alex) Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
277bd337 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: convert gfx.kiq to array type (v3) v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e78105c8 |
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02-Jan-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Remove superfluous assignment for `adev->mes.adev` `amdgpu_mes_init` already sets `adev->mes.adev`, so there is no need to also set it in the IP specific versions. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11e0b006 |
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03-Jan-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Use `amdgpu_ucode_*` helpers for MES The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper provides symmetry for releasing firmware. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cc42e76e |
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28-Dec-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Load MES microcode during early_init Add an early_init phase to MES for fetching and validating microcode from the filesystem. If MES microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for MES microcode into the early_init phase so that if it's not available, early_init will fail. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9a1662f5 |
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29-Sep-2022 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdgpu: extend halt_if_hws_hang to MES Hang on MES timeout if halt_if_hws_hang is set to 1. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6040517e |
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25-Oct-2022 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdgpu: remove deprecated MES version vars MES scheduler and kiq versions are stored in mes.sched_version and mes.kiq_version, respectively, which are read from a register after their queues are initialized. Remove mes.ucode_fw_version and mes.data_fw_version which tried to read this versioning info from the firmware headers (which don't contain this information). Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ed67f729 |
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20-Jul-2022 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: move mes self test after drm sched re-started mes self test rely on vm mapping, move it after drm sched re-started so that vm mapping can work during gpu reset. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-and-tested-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0fe69062 |
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29-Oct-2020 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/mes: init aggregated doorbell Allocate and enable aggregated doorbell. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
63677486 |
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08-Jul-2022 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: set correct mes ring ready flag Set corresponding ready flag for mes ring when enable or disable mes ring. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
35ba8850 |
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07-Jul-2022 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: fix mes submission in atomic context For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
12ec9a43 |
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04-Aug-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/gfx10: enable kiq to map mes ring Enable KIQ to map MES ring: 1). add MES queue mapping support in MAP_QUEUES packet. 2). use correct MQD settings for MES queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
18ee4ce6 |
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13-Apr-2022 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add mes unmap legacy queue routine For mes kiq has been taken over by mes sched, drv can't directly use mes kiq to unmap queues. drv has to use mes sched api to unmap legacy queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
21317335 |
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26-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add mes self test in late init Add MES self test in late init. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
29634c3f |
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16-Jun-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement the suspend/resume routine Implement the suspend/resume routine of mes. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7149599b |
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04-Jun-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add delay after mes engine enable Add delay after mes engine enable, for it needs more time to complete engine initialising. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4df80927 |
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25-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: call general mes initialization Call general mes initialization/finalization. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0bf478f0 |
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28-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: relocate status_fence slot allocation Move the status_fence slot allocation from ip specific function to general mes function. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f10e80e3 |
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14-Apr-2021 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: enable mes kiq N-1 test on sienna cichlid Enable kiq support on gfx10.3, enable mes kiq (n-1) test on sienna cichlid, so that mes kiq can be tested on sienna cichlid. The patch can be dropped once mes kiq is functional. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
207e8bbe |
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14-Apr-2021 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes: extend mes framework to support multiple mes pipes Add support for multiple mes pipes, so that reuse the existing code to initialize more mes pipe and queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3748424b |
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19-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: use ring structure to access rptr/wptr v2 Use ring structure to access the cpu/gpu address of rptr/wptr. v2: merge gfx10/sdma5/sdma5.2 patches Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c107171b |
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02-Feb-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add the sched_score to amdgpu_ring_init Allow separate ring to share the same scheduler score. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e11bfb99 |
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09-Dec-2020 |
Christian König <christian.koenig@amd.com> |
drm/ttm: cleanup BO size handling v3 Based on an idea from Dave, but cleaned up a bit. We had multiple fields for essentially the same thing. Now bo->base.size is the original size of the BO in arbitrary units, usually bytes. bo->mem.num_pages is the size in number of pages in the resource domain of bo->mem.mem_type. v2: use the GEM object size instead of the BO size v3: fix printks in some places Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> (v1) Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/406831/
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#
8acedab0 |
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02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu: use "*" adjacent to data name When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d94c8250 |
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21-Sep-2020 |
Qinglang Miao <miaoqinglang@huawei.com> |
drm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_init Simplify the return expression. Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1e09dfd7 |
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09-Apr-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/mes10.1: add no scheduler flag for mes We don't want a gpu scheduler for mes. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7cf609b9 |
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20-Mar-2020 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/mes: allocate memory slots for hw resource setting Pass a piece of memory to MES ucode to fill contents. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ae4e3b62 |
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20-Mar-2020 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/mes: add status fence memory definitions Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25fc0564 |
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20-Nov-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/mes: correct register offset for sienna_cichlid Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9ed60748 |
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15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: update mes initialization Update mes initialization sequence. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6b8199fc |
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06-Jun-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: copy mes fw info into global fw array Copy mes firmware info into into global fw array, preparing for fw front door loading. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f85f1864 |
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15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support Add sienna_cichlid mes firmware support. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7a9b4fd4 |
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15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement setting hardware resources The routine is implemented to generate mes command to assign the hardware resources which can be scheduled to mes. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3e62add5 |
|
15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement querying the scheduler status The routine is implemented to generate mes command to query the status of hardware scheduler. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bc2a2812 |
|
15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement removing hardware queue The routine is implemented to generate mes command to remove a specified hardware queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e8bb73e0 |
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15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement adding hardware queue The routine is implemented to generate mes command to install a hardware queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
29ce0f6f |
|
15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add the helper function for mes command submission The helper function is used to submit mes command and poll waiting for the command completion. v2: replaced with amdgpu_fence_wait_polling to wait. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3f63345d |
|
15-Oct-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add the mes fw api Add the definitions of mes commands. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e25c0dcd |
|
29-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: enable the mes ring during initialization Enable the mes ring during mes block initialization. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c0d96b0 |
|
29-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: install mes queue via kiq Install mes queue via kiq. Disable it temporarily until it's workable. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
debce56d |
|
29-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: install mes queue by register programming Directly writing mes queue registers to set up it. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
74d250fb |
|
29-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: initialize the mqd Initialize the mqd according to mes ring setup. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
52d6bb12 |
|
05-Jun-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: allocate mqd buffer Allocate mqd buffer preparing for mes queue setup. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1513e24a |
|
05-Jun-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement the ring functions of mes specific Implement mes ring functions and set up them. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7b2513a1 |
|
26-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: initialize the software part of mes ring Do the software initialization on the mes ring. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11f6f11d |
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05-Jun-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: allocate the eop buffer eop buffer will be used for mes queue setup. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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77657ad1 |
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15-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: enable mes FW backdoor loading It enables MES FW backdoor loading in ip block functions. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5c264af7 |
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14-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement mes enablement function After MES firmware gets loaded, it enables MES engine starting execution. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fb19a68d |
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14-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement MES firmware backdoor loading It implements MES firmware backdoor loading. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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71c57941 |
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12-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement ucode buffers destruction Free ucode GPU buffers. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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85c90e9b |
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12-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: upload mes data ucode to gpu buffer Allocate GPU buffer and upload mes data ucode to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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02b61149 |
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12-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: upload mes ucode to gpu buffer Allocate GPU buffer and upload ucode firmware to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
08698105 |
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15-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: implement ucode CPU buffer destruction It implements the CPU buffer destruction of ucode. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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298d0546 |
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14-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: load mes firmware file to CPU buffer It requests MES firmware binary and uploads to CPU buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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886f82aa |
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25-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/mes10.1: add ip block mes10.1 (v2) MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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