Searched refs:wptr (Results 26 - 50 of 137) sorted by relevance

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/linux-master/drivers/gpu/drm/radeon/
H A Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr);
100 WREG32(VCE_RB_WPTR2, ring->wptr);
298 WREG32(VCE_RB_RPTR, ring->wptr);
299 WREG32(VCE_RB_WPTR, ring->wptr);
305 WREG32(VCE_RB_RPTR2, ring->wptr);
306 WREG32(VCE_RB_WPTR2, ring->wptr);
H A Dr600_dma.c69 * Get the current wptr from the hardware (r6xx+).
83 * Write the wptr back to the hardware (r6xx+).
88 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
166 ring->wptr = 0;
167 WREG32(DMA_RB_WPTR, ring->wptr << 2);
409 u32 next_rptr = ring->wptr + 4;
422 while ((ring->wptr & 7) != 5)
H A Dni_dma.c77 * Get the current wptr from the hardware (cayman+).
98 * Write the wptr back to the hardware (cayman+).
110 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
128 u32 next_rptr = ring->wptr + 4;
141 while ((ring->wptr & 7) != 5)
242 ring->wptr = 0;
243 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
H A Devergreen_dma.c72 u32 next_rptr = ring->wptr + 4;
85 while ((ring->wptr & 7) != 5)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c262 ret = ring->wptr & ring->buf_mask;
292 * Get the current wptr from the hardware (NAVI10+).
297 u64 wptr; local
301 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
302 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
304 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
305 wptr = wptr << 32;
306 wptr |
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H A Damdgpu_ring_mux.c212 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) argument
228 /* We could skip this set wptr as preemption in process. */
238 e->sw_wptr = wptr;
239 e->start_ptr_in_hw_ring = mux->real_ring->wptr;
242 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) {
243 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr);
244 e->end_ptr_in_hw_ring = mux->real_ring->wptr;
247 e->end_ptr_in_hw_ring = mux->real_ring->wptr;
339 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr);
427 offset = ring->wptr
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H A Dvcn_v2_0.c919 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
921 lower_32_bits(ring->wptr));
1077 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1079 lower_32_bits(ring->wptr));
1084 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1085 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1093 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1094 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1237 ring->wptr = 0;
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
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H A Dvega10_ih.c123 /* set rptr, wptr to 0 */
241 /* set rptr, wptr to 0 */
325 * vega10_ih_get_wptr - get the IH ring buffer wptr
328 * @ih: IH ring buffer to fetch wptr
330 * Get the IH ring buffer wptr from either the register
333 * Returns the value of the wptr.
338 u32 wptr, tmp; local
345 * update wptr and return.
347 wptr = le32_to_cpu(*ih->wptr_cpu);
349 if (!REG_GET_FIELD(wptr, IH_RB_WPT
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H A Dnavi10_ih.c90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
93 * @threshold: threshold to trigger the wptr reporting
94 * @timeout: timeout to trigger the wptr reporting
102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
178 /* set rptr, wptr to 0 */
297 /* set rptr, wptr to 0 */
370 /* enable wptr force update for self int */
396 * navi10_ih_get_wptr - get the IH ring buffer wptr
399 * @ih: IH ring buffer to fetch wptr
401 * Get the IH ring buffer wptr fro
409 u32 wptr, tmp; local
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H A Dvega20_ih.c132 /* set rptr, wptr to 0 */
250 /* set rptr, wptr to 0 */
375 * vega20_ih_get_wptr - get the IH ring buffer wptr
380 * Get the IH ring buffer wptr from either the register
383 * Returns the value of the wptr.
388 u32 wptr, tmp; local
395 * update wptr and return.
397 wptr = le32_to_cpu(*ih->wptr_cpu);
399 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
406 wptr
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H A Dvcn_v3_0.c319 ring->wptr = 0;
332 ring->wptr = 0;
1078 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1080 lower_32_bits(ring->wptr));
1084 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1254 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1256 lower_32_bits(ring->wptr));
1257 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
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H A Dvce_v2_0.c94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
244 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
251 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
252 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
H A Damdgpu_amdkfd_gc_9_4_3.c60 uint32_t __user *wptr, struct mm_struct *mm)
67 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
286 uint32_t __user *wptr, uint32_t wptr_shift,
311 if (wptr) {
312 /* Don't read wptr with get_user because the user
316 * that wptr is GPU-accessible in the queue's VMID via
343 lower_32_bits((uintptr_t)wptr));
345 upper_32_bits((uintptr_t)wptr));
59 kgd_gfx_v9_4_3_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) argument
284 kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) argument
H A Dsdma_v4_0.c622 * Get the current wptr from the hardware (VEGA10+).
627 u64 wptr; local
631 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
632 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
634 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
635 wptr = wptr << 32;
636 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
637 DRM_DEBUG("wptr befor
696 u64 wptr; local
728 uint64_t wptr = ring->wptr << 2; local
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H A Dsdma_v5_2.c102 ret = ring->wptr & ring->buf_mask;
132 * Get the current wptr from the hardware (NAVI10+).
137 u64 wptr; local
141 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
142 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
144 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
145 wptr = wptr << 32;
146 wptr |
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H A Damdgpu_ring_mux.h108 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr);
H A Dvce_v4_0.c109 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
110 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
116 lower_32_bits(ring->wptr));
119 lower_32_bits(ring->wptr));
122 lower_32_bits(ring->wptr));
181 adev->vce.ring[0].wptr = 0;
343 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
344 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
351 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));
352 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));
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H A Damdgpu_ring.h251 u64 wptr; member in struct:amdgpu_ring
379 ring->ring[ring->wptr++ & ring->buf_mask] = v;
380 ring->wptr &= ring->ptr_mask;
393 occupied = ring->wptr & ring->buf_mask;
410 ring->wptr += count_dw;
411 ring->wptr &= ring->ptr_mask;
433 cur = (ring->wptr - 1) & ring->buf_mask;
H A Dvcn_v1_0.c937 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
939 lower_32_bits(ring->wptr));
945 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
946 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
952 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
953 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1095 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1097 lower_32_bits(ring->wptr));
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
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H A Dsdma_v6_0.c93 ret = ring->wptr & ring->buf_mask;
123 * Get the current wptr from the hardware.
127 u64 wptr = 0; local
131 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
132 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
135 return wptr >> 2;
143 * Write the wptr back to the hardware.
152 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
153 "upper_32_bits(ring->wptr) <<
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H A Dvcn_v2_5.c954 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
956 lower_32_bits(ring->wptr));
1132 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1134 lower_32_bits(ring->wptr));
1139 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1140 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1148 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1149 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1309 ring->wptr = 0;
1322 ring->wptr
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/linux-master/drivers/tty/serial/
H A Dmen_z135_uart.c298 u32 wptr; local
320 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
321 txc = (wptr >> 16) & 0x3ff;
322 wptr &= 0x3ff;
338 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
339 n = 4 - BYTES_TO_ALIGN(wptr);
456 u32 wptr; local
459 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
460 txc = (wptr >> 16) & 0x3ff;
/linux-master/drivers/media/platform/amphion/
H A Dvpu_helpers.h27 u32 *wptr, u32 size, void *src);
29 u32 *wptr, u8 val, u32 size);
H A Dvpu_dbg.c284 "cmd_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n",
287 iface->cmd_desc->wptr,
292 "msg_buf:[0x%x, 0x%x], wptr = 0x%x, rptr = 0x%x\n",
295 iface->msg_desc->wptr,
309 u32 wptr; local
317 wptr = print_buf->write;
319 if (rptr == wptr)
321 else if (rptr < wptr)
322 length = wptr - rptr;
324 length = print_buf->bytes + wptr
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/linux-master/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.c625 uint32_t wptr; local
631 * Mask wptr value that we calculate to fit in the HW range. This is
635 wptr = get_wptr(ring);
640 gpu_write(gpu, reg, wptr);
646 uint32_t wptr = get_wptr(ring); local
649 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
653 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
654 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
677 state->ring[i].wptr = get_wptr(gpu->rb[i]);
679 /* Copy at least 'wptr' dword
964 uint32_t wptr = ring->next - ring->start; local
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