Lines Matching refs:wptr

262 	ret = ring->wptr & ring->buf_mask;
292 * Get the current wptr from the hardware (NAVI10+).
297 u64 wptr;
301 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
302 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
304 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
305 wptr = wptr << 32;
306 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
307 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
310 return wptr >> 2;
318 * Write the wptr back to the hardware (NAVI10+).
338 ring->wptr << 2);
339 *wptr_saved = ring->wptr << 2;
341 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
343 ring->doorbell_index, ring->wptr << 2);
344 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
347 ring->doorbell_index, ring->wptr << 2);
348 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
352 ring->wptr << 2);
358 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
359 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
361 lower_32_bits(ring->wptr << 2),
362 upper_32_bits(ring->wptr << 2));
365 ring->wptr << 2);
367 ring->doorbell_index, ring->wptr << 2);
368 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
374 lower_32_bits(ring->wptr << 2),
376 upper_32_bits(ring->wptr << 2));
379 lower_32_bits(ring->wptr << 2));
382 upper_32_bits(ring->wptr << 2));
422 * wptr + 6 + x = 8k, k >= 0, which in C is,
423 * (wptr + 6 + x) % 8 = 0.
426 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
701 /* setup the wptr shadow polling */
728 ring->wptr = 0;
730 /* before programing wptr to a less value, need set minor_ptr_update first */
733 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
735 lower_32_bits(ring->wptr << 2));
737 upper_32_bits(ring->wptr << 2));
761 /* set minor_ptr_update to 0 after wptr programed */