1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/pci.h> 25 26#include "amdgpu.h" 27#include "amdgpu_ih.h" 28#include "soc15.h" 29 30#include "oss/osssys_4_0_offset.h" 31#include "oss/osssys_4_0_sh_mask.h" 32 33#include "soc15_common.h" 34#include "vega10_ih.h" 35 36#define MAX_REARM_RETRY 10 37 38static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39 40/** 41 * vega10_ih_init_register_offset - Initialize register offset for ih rings 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Initialize register offset ih rings (VEGA10). 46 */ 47static void vega10_ih_init_register_offset(struct amdgpu_device *adev) 48{ 49 struct amdgpu_ih_regs *ih_regs; 50 51 if (adev->irq.ih.ring_size) { 52 ih_regs = &adev->irq.ih.ih_regs; 53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62 } 63 64 if (adev->irq.ih1.ring_size) { 65 ih_regs = &adev->irq.ih1.ih_regs; 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73 } 74 75 if (adev->irq.ih2.ring_size) { 76 ih_regs = &adev->irq.ih2.ih_regs; 77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84 } 85} 86 87/** 88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89 * 90 * @adev: amdgpu_device pointer 91 * @ih: amdgpu_ih_ring pointet 92 * @enable: true - enable the interrupts, false - disable the interrupts 93 * 94 * Toggle the interrupt ring buffer (VEGA10) 95 */ 96static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97 struct amdgpu_ih_ring *ih, 98 bool enable) 99{ 100 struct amdgpu_ih_regs *ih_regs; 101 uint32_t tmp; 102 103 ih_regs = &ih->ih_regs; 104 105 tmp = RREG32(ih_regs->ih_rb_cntl); 106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 108 /* enable_intr field is only valid in ring0 */ 109 if (ih == &adev->irq.ih) 110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 111 if (amdgpu_sriov_vf(adev)) { 112 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 113 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 114 return -ETIMEDOUT; 115 } 116 } else { 117 WREG32(ih_regs->ih_rb_cntl, tmp); 118 } 119 120 if (enable) { 121 ih->enabled = true; 122 } else { 123 /* set rptr, wptr to 0 */ 124 WREG32(ih_regs->ih_rb_rptr, 0); 125 WREG32(ih_regs->ih_rb_wptr, 0); 126 ih->enabled = false; 127 ih->rptr = 0; 128 } 129 130 return 0; 131} 132 133/** 134 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 135 * 136 * @adev: amdgpu_device pointer 137 * @enable: enable or disable interrupt ring buffers 138 * 139 * Toggle all the available interrupt ring buffers (VEGA10). 140 */ 141static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 142{ 143 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 144 int i; 145 int r; 146 147 for (i = 0; i < ARRAY_SIZE(ih); i++) { 148 if (ih[i]->ring_size) { 149 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); 150 if (r) 151 return r; 152 } 153 } 154 155 return 0; 156} 157 158static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 159{ 160 int rb_bufsz = order_base_2(ih->ring_size / 4); 161 162 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 163 MC_SPACE, ih->use_bus_addr ? 1 : 4); 164 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 165 WPTR_OVERFLOW_CLEAR, 1); 166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167 WPTR_OVERFLOW_ENABLE, 1); 168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 169 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 170 * value is written to memory 171 */ 172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173 WPTR_WRITEBACK_ENABLE, 1); 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 177 178 return ih_rb_cntl; 179} 180 181static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 182{ 183 u32 ih_doorbell_rtpr = 0; 184 185 if (ih->use_doorbell) { 186 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 187 IH_DOORBELL_RPTR, OFFSET, 188 ih->doorbell_index); 189 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 190 IH_DOORBELL_RPTR, 191 ENABLE, 1); 192 } else { 193 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 194 IH_DOORBELL_RPTR, 195 ENABLE, 0); 196 } 197 return ih_doorbell_rtpr; 198} 199 200/** 201 * vega10_ih_enable_ring - enable an ih ring buffer 202 * 203 * @adev: amdgpu_device pointer 204 * @ih: amdgpu_ih_ring pointer 205 * 206 * Enable an ih ring buffer (VEGA10) 207 */ 208static int vega10_ih_enable_ring(struct amdgpu_device *adev, 209 struct amdgpu_ih_ring *ih) 210{ 211 struct amdgpu_ih_regs *ih_regs; 212 uint32_t tmp; 213 214 ih_regs = &ih->ih_regs; 215 216 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 217 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 218 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 219 220 tmp = RREG32(ih_regs->ih_rb_cntl); 221 tmp = vega10_ih_rb_cntl(ih, tmp); 222 if (ih == &adev->irq.ih) 223 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 224 if (ih == &adev->irq.ih1) 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226 if (amdgpu_sriov_vf(adev)) { 227 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 228 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 229 return -ETIMEDOUT; 230 } 231 } else { 232 WREG32(ih_regs->ih_rb_cntl, tmp); 233 } 234 235 if (ih == &adev->irq.ih) { 236 /* set the ih ring 0 writeback address whether it's enabled or not */ 237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 239 } 240 241 /* set rptr, wptr to 0 */ 242 WREG32(ih_regs->ih_rb_wptr, 0); 243 WREG32(ih_regs->ih_rb_rptr, 0); 244 245 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); 246 247 return 0; 248} 249 250/** 251 * vega10_ih_irq_init - init and enable the interrupt ring 252 * 253 * @adev: amdgpu_device pointer 254 * 255 * Allocate a ring buffer for the interrupt controller, 256 * enable the RLC, disable interrupts, enable the IH 257 * ring buffer and enable it (VI). 258 * Called at device load and reume. 259 * Returns 0 for success, errors for failure. 260 */ 261static int vega10_ih_irq_init(struct amdgpu_device *adev) 262{ 263 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 264 u32 ih_chicken; 265 int ret; 266 int i; 267 268 /* disable irqs */ 269 ret = vega10_ih_toggle_interrupts(adev, false); 270 if (ret) 271 return ret; 272 273 adev->nbio.funcs->ih_control(adev); 274 275 if (adev->asic_type == CHIP_RENOIR) { 276 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 277 if (adev->irq.ih.use_bus_addr) { 278 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 279 MC_SPACE_GPA_ENABLE, 1); 280 } 281 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 282 } 283 284 for (i = 0; i < ARRAY_SIZE(ih); i++) { 285 if (ih[i]->ring_size) { 286 ret = vega10_ih_enable_ring(adev, ih[i]); 287 if (ret) 288 return ret; 289 } 290 } 291 292 if (!amdgpu_sriov_vf(adev)) 293 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 294 adev->irq.ih.doorbell_index); 295 296 pci_set_master(adev->pdev); 297 298 /* enable interrupts */ 299 ret = vega10_ih_toggle_interrupts(adev, true); 300 if (ret) 301 return ret; 302 303 if (adev->irq.ih_soft.ring_size) 304 adev->irq.ih_soft.enabled = true; 305 306 return 0; 307} 308 309/** 310 * vega10_ih_irq_disable - disable interrupts 311 * 312 * @adev: amdgpu_device pointer 313 * 314 * Disable interrupts on the hw (VEGA10). 315 */ 316static void vega10_ih_irq_disable(struct amdgpu_device *adev) 317{ 318 vega10_ih_toggle_interrupts(adev, false); 319 320 /* Wait and acknowledge irq */ 321 mdelay(1); 322} 323 324/** 325 * vega10_ih_get_wptr - get the IH ring buffer wptr 326 * 327 * @adev: amdgpu_device pointer 328 * @ih: IH ring buffer to fetch wptr 329 * 330 * Get the IH ring buffer wptr from either the register 331 * or the writeback memory buffer (VEGA10). Also check for 332 * ring buffer overflow and deal with it. 333 * Returns the value of the wptr. 334 */ 335static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, 336 struct amdgpu_ih_ring *ih) 337{ 338 u32 wptr, tmp; 339 struct amdgpu_ih_regs *ih_regs; 340 341 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 342 /* Only ring0 supports writeback. On other rings fall back 343 * to register-based code with overflow checking below. 344 * ih_soft ring doesn't have any backing hardware registers, 345 * update wptr and return. 346 */ 347 wptr = le32_to_cpu(*ih->wptr_cpu); 348 349 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 350 goto out; 351 } 352 353 ih_regs = &ih->ih_regs; 354 355 /* Double check that the overflow wasn't already cleared. */ 356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 357 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 358 goto out; 359 360 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 361 362 /* When a ring buffer overflow happen start parsing interrupt 363 * from the last not overwritten vector (wptr + 32). Hopefully 364 * this should allow us to catchup. 365 */ 366 tmp = (wptr + 32) & ih->ptr_mask; 367 dev_warn(adev->dev, "IH ring buffer overflow " 368 "(0x%08X, 0x%08X, 0x%08X)\n", 369 wptr, ih->rptr, tmp); 370 ih->rptr = tmp; 371 372 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 373 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 374 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 375 376 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 377 * can be detected. 378 */ 379 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 380 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 381 382out: 383 return (wptr & ih->ptr_mask); 384} 385 386/** 387 * vega10_ih_irq_rearm - rearm IRQ if lost 388 * 389 * @adev: amdgpu_device pointer 390 * @ih: IH ring to match 391 * 392 */ 393static void vega10_ih_irq_rearm(struct amdgpu_device *adev, 394 struct amdgpu_ih_ring *ih) 395{ 396 uint32_t v = 0; 397 uint32_t i = 0; 398 struct amdgpu_ih_regs *ih_regs; 399 400 ih_regs = &ih->ih_regs; 401 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 402 for (i = 0; i < MAX_REARM_RETRY; i++) { 403 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 404 if ((v < ih->ring_size) && (v != ih->rptr)) 405 WDOORBELL32(ih->doorbell_index, ih->rptr); 406 else 407 break; 408 } 409} 410 411/** 412 * vega10_ih_set_rptr - set the IH ring buffer rptr 413 * 414 * @adev: amdgpu_device pointer 415 * @ih: IH ring buffer to set rptr 416 * 417 * Set the IH ring buffer rptr. 418 */ 419static void vega10_ih_set_rptr(struct amdgpu_device *adev, 420 struct amdgpu_ih_ring *ih) 421{ 422 struct amdgpu_ih_regs *ih_regs; 423 424 if (ih == &adev->irq.ih_soft) 425 return; 426 427 if (ih->use_doorbell) { 428 /* XXX check if swapping is necessary on BE */ 429 *ih->rptr_cpu = ih->rptr; 430 WDOORBELL32(ih->doorbell_index, ih->rptr); 431 432 if (amdgpu_sriov_vf(adev)) 433 vega10_ih_irq_rearm(adev, ih); 434 } else { 435 ih_regs = &ih->ih_regs; 436 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 437 } 438} 439 440/** 441 * vega10_ih_self_irq - dispatch work for ring 1 and 2 442 * 443 * @adev: amdgpu_device pointer 444 * @source: irq source 445 * @entry: IV with WPTR update 446 * 447 * Update the WPTR from the IV and schedule work to handle the entries. 448 */ 449static int vega10_ih_self_irq(struct amdgpu_device *adev, 450 struct amdgpu_irq_src *source, 451 struct amdgpu_iv_entry *entry) 452{ 453 switch (entry->ring_id) { 454 case 1: 455 schedule_work(&adev->irq.ih1_work); 456 break; 457 case 2: 458 schedule_work(&adev->irq.ih2_work); 459 break; 460 default: break; 461 } 462 return 0; 463} 464 465static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = { 466 .process = vega10_ih_self_irq, 467}; 468 469static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 470{ 471 adev->irq.self_irq.num_types = 0; 472 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; 473} 474 475static int vega10_ih_early_init(void *handle) 476{ 477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478 479 vega10_ih_set_interrupt_funcs(adev); 480 vega10_ih_set_self_irq_funcs(adev); 481 return 0; 482} 483 484static int vega10_ih_sw_init(void *handle) 485{ 486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 487 int r; 488 489 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 490 &adev->irq.self_irq); 491 if (r) 492 return r; 493 494 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true); 495 if (r) 496 return r; 497 498 adev->irq.ih.use_doorbell = true; 499 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 500 501 if (!(adev->flags & AMD_IS_APU)) { 502 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 503 if (r) 504 return r; 505 506 adev->irq.ih1.use_doorbell = true; 507 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 508 509 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 510 if (r) 511 return r; 512 513 adev->irq.ih2.use_doorbell = true; 514 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 515 } 516 /* initialize ih control registers offset */ 517 vega10_ih_init_register_offset(adev); 518 519 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); 520 if (r) 521 return r; 522 523 r = amdgpu_irq_init(adev); 524 525 return r; 526} 527 528static int vega10_ih_sw_fini(void *handle) 529{ 530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 531 532 amdgpu_irq_fini_sw(adev); 533 534 return 0; 535} 536 537static int vega10_ih_hw_init(void *handle) 538{ 539 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 540 541 return vega10_ih_irq_init(adev); 542} 543 544static int vega10_ih_hw_fini(void *handle) 545{ 546 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 547 548 vega10_ih_irq_disable(adev); 549 550 return 0; 551} 552 553static int vega10_ih_suspend(void *handle) 554{ 555 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 556 557 return vega10_ih_hw_fini(adev); 558} 559 560static int vega10_ih_resume(void *handle) 561{ 562 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 563 564 return vega10_ih_hw_init(adev); 565} 566 567static bool vega10_ih_is_idle(void *handle) 568{ 569 /* todo */ 570 return true; 571} 572 573static int vega10_ih_wait_for_idle(void *handle) 574{ 575 /* todo */ 576 return -ETIMEDOUT; 577} 578 579static int vega10_ih_soft_reset(void *handle) 580{ 581 /* todo */ 582 583 return 0; 584} 585 586static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev, 587 bool enable) 588{ 589 uint32_t data, def, field_val; 590 591 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 592 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 593 field_val = enable ? 0 : 1; 594 /** 595 * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field. 596 */ 597 if (adev->asic_type == CHIP_RENOIR) 598 data = REG_SET_FIELD(data, IH_CLK_CTRL, 599 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 600 601 data = REG_SET_FIELD(data, IH_CLK_CTRL, 602 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 603 data = REG_SET_FIELD(data, IH_CLK_CTRL, 604 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 605 data = REG_SET_FIELD(data, IH_CLK_CTRL, 606 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 607 data = REG_SET_FIELD(data, IH_CLK_CTRL, 608 DYN_CLK_SOFT_OVERRIDE, field_val); 609 data = REG_SET_FIELD(data, IH_CLK_CTRL, 610 REG_CLK_SOFT_OVERRIDE, field_val); 611 if (def != data) 612 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 613 } 614} 615 616static int vega10_ih_set_clockgating_state(void *handle, 617 enum amd_clockgating_state state) 618{ 619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 620 621 vega10_ih_update_clockgating_state(adev, 622 state == AMD_CG_STATE_GATE); 623 return 0; 624 625} 626 627static int vega10_ih_set_powergating_state(void *handle, 628 enum amd_powergating_state state) 629{ 630 return 0; 631} 632 633const struct amd_ip_funcs vega10_ih_ip_funcs = { 634 .name = "vega10_ih", 635 .early_init = vega10_ih_early_init, 636 .late_init = NULL, 637 .sw_init = vega10_ih_sw_init, 638 .sw_fini = vega10_ih_sw_fini, 639 .hw_init = vega10_ih_hw_init, 640 .hw_fini = vega10_ih_hw_fini, 641 .suspend = vega10_ih_suspend, 642 .resume = vega10_ih_resume, 643 .is_idle = vega10_ih_is_idle, 644 .wait_for_idle = vega10_ih_wait_for_idle, 645 .soft_reset = vega10_ih_soft_reset, 646 .set_clockgating_state = vega10_ih_set_clockgating_state, 647 .set_powergating_state = vega10_ih_set_powergating_state, 648}; 649 650static const struct amdgpu_ih_funcs vega10_ih_funcs = { 651 .get_wptr = vega10_ih_get_wptr, 652 .decode_iv = amdgpu_ih_decode_iv_helper, 653 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 654 .set_rptr = vega10_ih_set_rptr 655}; 656 657static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 658{ 659 adev->irq.ih_funcs = &vega10_ih_funcs; 660} 661 662const struct amdgpu_ip_block_version vega10_ih_ip_block = 663{ 664 .type = AMD_IP_BLOCK_TYPE_IH, 665 .major = 4, 666 .minor = 0, 667 .rev = 0, 668 .funcs = &vega10_ih_ip_funcs, 669}; 670