1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/pci.h> 25 26#include "amdgpu.h" 27#include "amdgpu_ih.h" 28#include "soc15.h" 29 30#include "oss/osssys_4_2_0_offset.h" 31#include "oss/osssys_4_2_0_sh_mask.h" 32 33#include "soc15_common.h" 34#include "vega20_ih.h" 35 36#define MAX_REARM_RETRY 10 37 38#define mmIH_CHICKEN_ALDEBARAN 0x18d 39#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40 41#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea 42#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0 43#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10 44#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L 45 46static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 47 48/** 49 * vega20_ih_init_register_offset - Initialize register offset for ih rings 50 * 51 * @adev: amdgpu_device pointer 52 * 53 * Initialize register offset ih rings (VEGA20). 54 */ 55static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 56{ 57 struct amdgpu_ih_regs *ih_regs; 58 59 if (adev->irq.ih.ring_size) { 60 ih_regs = &adev->irq.ih.ih_regs; 61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 70 } 71 72 if (adev->irq.ih1.ring_size) { 73 ih_regs = &adev->irq.ih1.ih_regs; 74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 81 } 82 83 if (adev->irq.ih2.ring_size) { 84 ih_regs = &adev->irq.ih2.ih_regs; 85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 92 } 93} 94 95/** 96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 97 * 98 * @adev: amdgpu_device pointer 99 * @ih: amdgpu_ih_ring pointer 100 * @enable: true - enable the interrupts, false - disable the interrupts 101 * 102 * Toggle the interrupt ring buffer (VEGA20) 103 */ 104static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 105 struct amdgpu_ih_ring *ih, 106 bool enable) 107{ 108 struct amdgpu_ih_regs *ih_regs; 109 uint32_t tmp; 110 111 ih_regs = &ih->ih_regs; 112 113 tmp = RREG32(ih_regs->ih_rb_cntl); 114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 116 117 /* enable_intr field is only valid in ring0 */ 118 if (ih == &adev->irq.ih) 119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 120 if (amdgpu_sriov_vf(adev)) { 121 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 122 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 123 return -ETIMEDOUT; 124 } 125 } else { 126 WREG32(ih_regs->ih_rb_cntl, tmp); 127 } 128 129 if (enable) { 130 ih->enabled = true; 131 } else { 132 /* set rptr, wptr to 0 */ 133 WREG32(ih_regs->ih_rb_rptr, 0); 134 WREG32(ih_regs->ih_rb_wptr, 0); 135 ih->enabled = false; 136 ih->rptr = 0; 137 } 138 139 return 0; 140} 141 142/** 143 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 144 * 145 * @adev: amdgpu_device pointer 146 * @enable: enable or disable interrupt ring buffers 147 * 148 * Toggle all the available interrupt ring buffers (VEGA20). 149 */ 150static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 151{ 152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 153 int i; 154 int r; 155 156 for (i = 0; i < ARRAY_SIZE(ih); i++) { 157 if (ih[i]->ring_size) { 158 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 159 if (r) 160 return r; 161 } 162 } 163 164 return 0; 165} 166 167static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 168{ 169 int rb_bufsz = order_base_2(ih->ring_size / 4); 170 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 MC_SPACE, ih->use_bus_addr ? 1 : 4); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174 WPTR_OVERFLOW_CLEAR, 1); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176 WPTR_OVERFLOW_ENABLE, 1); 177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 178 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 179 * value is written to memory 180 */ 181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 182 WPTR_WRITEBACK_ENABLE, 1); 183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 186 187 return ih_rb_cntl; 188} 189 190static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 191{ 192 u32 ih_doorbell_rtpr = 0; 193 194 if (ih->use_doorbell) { 195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 196 IH_DOORBELL_RPTR, OFFSET, 197 ih->doorbell_index); 198 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 199 IH_DOORBELL_RPTR, 200 ENABLE, 1); 201 } else { 202 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 203 IH_DOORBELL_RPTR, 204 ENABLE, 0); 205 } 206 return ih_doorbell_rtpr; 207} 208 209/** 210 * vega20_ih_enable_ring - enable an ih ring buffer 211 * 212 * @adev: amdgpu_device pointer 213 * @ih: amdgpu_ih_ring pointer 214 * 215 * Enable an ih ring buffer (VEGA20) 216 */ 217static int vega20_ih_enable_ring(struct amdgpu_device *adev, 218 struct amdgpu_ih_ring *ih) 219{ 220 struct amdgpu_ih_regs *ih_regs; 221 uint32_t tmp; 222 223 ih_regs = &ih->ih_regs; 224 225 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 226 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 227 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 228 229 tmp = RREG32(ih_regs->ih_rb_cntl); 230 tmp = vega20_ih_rb_cntl(ih, tmp); 231 if (ih == &adev->irq.ih) 232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 233 if (ih == &adev->irq.ih1) 234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 235 if (amdgpu_sriov_vf(adev)) { 236 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 237 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 238 return -ETIMEDOUT; 239 } 240 } else { 241 WREG32(ih_regs->ih_rb_cntl, tmp); 242 } 243 244 if (ih == &adev->irq.ih) { 245 /* set the ih ring 0 writeback address whether it's enabled or not */ 246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 248 } 249 250 /* set rptr, wptr to 0 */ 251 WREG32(ih_regs->ih_rb_wptr, 0); 252 WREG32(ih_regs->ih_rb_rptr, 0); 253 254 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 255 256 return 0; 257} 258 259static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index) 260{ 261 u32 val = 0; 262 263 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); 264 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); 265 266 return val; 267} 268 269/** 270 * vega20_ih_irq_init - init and enable the interrupt ring 271 * 272 * @adev: amdgpu_device pointer 273 * 274 * Allocate a ring buffer for the interrupt controller, 275 * enable the RLC, disable interrupts, enable the IH 276 * ring buffer and enable it (VI). 277 * Called at device load and reume. 278 * Returns 0 for success, errors for failure. 279 */ 280static int vega20_ih_irq_init(struct amdgpu_device *adev) 281{ 282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 283 u32 ih_chicken; 284 int ret; 285 int i; 286 287 /* disable irqs */ 288 ret = vega20_ih_toggle_interrupts(adev, false); 289 if (ret) 290 return ret; 291 292 adev->nbio.funcs->ih_control(adev); 293 294 if (!amdgpu_sriov_vf(adev)) { 295 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) && 296 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 297 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 298 if (adev->irq.ih.use_bus_addr) { 299 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 300 MC_SPACE_GPA_ENABLE, 1); 301 } 302 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 303 } 304 305 /* psp firmware won't program IH_CHICKEN for aldebaran 306 * driver needs to program it properly according to 307 * MC_SPACE type in IH_RB_CNTL */ 308 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) || 309 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) { 310 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 311 if (adev->irq.ih.use_bus_addr) { 312 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 313 MC_SPACE_GPA_ENABLE, 1); 314 } 315 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 316 } 317 } 318 319 for (i = 0; i < ARRAY_SIZE(ih); i++) { 320 if (ih[i]->ring_size) { 321 ret = vega20_ih_enable_ring(adev, ih[i]); 322 if (ret) 323 return ret; 324 } 325 } 326 327 if (!amdgpu_sriov_vf(adev)) 328 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 329 adev->irq.ih.doorbell_index); 330 331 pci_set_master(adev->pdev); 332 333 /* Allocate the doorbell for IH Retry CAM */ 334 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1; 335 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM, 336 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); 337 338 /* Enable IH Retry CAM */ 339 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) || 340 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) 341 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN, 342 ENABLE, 1); 343 else 344 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); 345 346 adev->irq.retry_cam_enabled = true; 347 348 /* enable interrupts */ 349 ret = vega20_ih_toggle_interrupts(adev, true); 350 if (ret) 351 return ret; 352 353 if (adev->irq.ih_soft.ring_size) 354 adev->irq.ih_soft.enabled = true; 355 356 return 0; 357} 358 359/** 360 * vega20_ih_irq_disable - disable interrupts 361 * 362 * @adev: amdgpu_device pointer 363 * 364 * Disable interrupts on the hw (VEGA20). 365 */ 366static void vega20_ih_irq_disable(struct amdgpu_device *adev) 367{ 368 vega20_ih_toggle_interrupts(adev, false); 369 370 /* Wait and acknowledge irq */ 371 mdelay(1); 372} 373 374/** 375 * vega20_ih_get_wptr - get the IH ring buffer wptr 376 * 377 * @adev: amdgpu_device pointer 378 * @ih: amdgpu_ih_ring pointer 379 * 380 * Get the IH ring buffer wptr from either the register 381 * or the writeback memory buffer (VEGA20). Also check for 382 * ring buffer overflow and deal with it. 383 * Returns the value of the wptr. 384 */ 385static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 386 struct amdgpu_ih_ring *ih) 387{ 388 u32 wptr, tmp; 389 struct amdgpu_ih_regs *ih_regs; 390 391 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 392 /* Only ring0 supports writeback. On other rings fall back 393 * to register-based code with overflow checking below. 394 * ih_soft ring doesn't have any backing hardware registers, 395 * update wptr and return. 396 */ 397 wptr = le32_to_cpu(*ih->wptr_cpu); 398 399 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 400 goto out; 401 } 402 403 ih_regs = &ih->ih_regs; 404 405 /* Double check that the overflow wasn't already cleared. */ 406 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 407 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 408 goto out; 409 410 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 411 412 /* When a ring buffer overflow happen start parsing interrupt 413 * from the last not overwritten vector (wptr + 32). Hopefully 414 * this should allow us to catchup. 415 */ 416 tmp = (wptr + 32) & ih->ptr_mask; 417 dev_warn(adev->dev, "IH ring buffer overflow " 418 "(0x%08X, 0x%08X, 0x%08X)\n", 419 wptr, ih->rptr, tmp); 420 ih->rptr = tmp; 421 422 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 423 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 424 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 425 426 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 427 * can be detected. 428 */ 429 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 430 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 431 432out: 433 return (wptr & ih->ptr_mask); 434} 435 436/** 437 * vega20_ih_irq_rearm - rearm IRQ if lost 438 * 439 * @adev: amdgpu_device pointer 440 * @ih: amdgpu_ih_ring pointer 441 * 442 */ 443static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 444 struct amdgpu_ih_ring *ih) 445{ 446 uint32_t v = 0; 447 uint32_t i = 0; 448 struct amdgpu_ih_regs *ih_regs; 449 450 ih_regs = &ih->ih_regs; 451 452 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 453 for (i = 0; i < MAX_REARM_RETRY; i++) { 454 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 455 if ((v < ih->ring_size) && (v != ih->rptr)) 456 WDOORBELL32(ih->doorbell_index, ih->rptr); 457 else 458 break; 459 } 460} 461 462/** 463 * vega20_ih_set_rptr - set the IH ring buffer rptr 464 * 465 * @adev: amdgpu_device pointer 466 * @ih: amdgpu_ih_ring pointer 467 * 468 * Set the IH ring buffer rptr. 469 */ 470static void vega20_ih_set_rptr(struct amdgpu_device *adev, 471 struct amdgpu_ih_ring *ih) 472{ 473 struct amdgpu_ih_regs *ih_regs; 474 475 if (ih == &adev->irq.ih_soft) 476 return; 477 478 if (ih->use_doorbell) { 479 /* XXX check if swapping is necessary on BE */ 480 *ih->rptr_cpu = ih->rptr; 481 WDOORBELL32(ih->doorbell_index, ih->rptr); 482 483 if (amdgpu_sriov_vf(adev)) 484 vega20_ih_irq_rearm(adev, ih); 485 } else { 486 ih_regs = &ih->ih_regs; 487 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 488 } 489} 490 491/** 492 * vega20_ih_self_irq - dispatch work for ring 1 and 2 493 * 494 * @adev: amdgpu_device pointer 495 * @source: irq source 496 * @entry: IV with WPTR update 497 * 498 * Update the WPTR from the IV and schedule work to handle the entries. 499 */ 500static int vega20_ih_self_irq(struct amdgpu_device *adev, 501 struct amdgpu_irq_src *source, 502 struct amdgpu_iv_entry *entry) 503{ 504 switch (entry->ring_id) { 505 case 1: 506 schedule_work(&adev->irq.ih1_work); 507 break; 508 case 2: 509 schedule_work(&adev->irq.ih2_work); 510 break; 511 default: 512 break; 513 } 514 return 0; 515} 516 517static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 518 .process = vega20_ih_self_irq, 519}; 520 521static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 522{ 523 adev->irq.self_irq.num_types = 0; 524 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 525} 526 527static int vega20_ih_early_init(void *handle) 528{ 529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530 531 vega20_ih_set_interrupt_funcs(adev); 532 vega20_ih_set_self_irq_funcs(adev); 533 return 0; 534} 535 536static int vega20_ih_sw_init(void *handle) 537{ 538 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 539 bool use_bus_addr = true; 540 int r; 541 542 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 543 &adev->irq.self_irq); 544 if (r) 545 return r; 546 547 if ((adev->flags & AMD_IS_APU) && 548 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) 549 use_bus_addr = false; 550 551 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); 552 if (r) 553 return r; 554 555 adev->irq.ih.use_doorbell = true; 556 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 557 558 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr); 559 if (r) 560 return r; 561 562 adev->irq.ih1.use_doorbell = true; 563 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 564 565 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2)) { 566 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 567 if (r) 568 return r; 569 570 adev->irq.ih2.use_doorbell = true; 571 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 572 } 573 574 /* initialize ih control registers offset */ 575 vega20_ih_init_register_offset(adev); 576 577 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr); 578 if (r) 579 return r; 580 581 r = amdgpu_irq_init(adev); 582 583 return r; 584} 585 586static int vega20_ih_sw_fini(void *handle) 587{ 588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 589 590 amdgpu_irq_fini_sw(adev); 591 592 return 0; 593} 594 595static int vega20_ih_hw_init(void *handle) 596{ 597 int r; 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 r = vega20_ih_irq_init(adev); 601 if (r) 602 return r; 603 604 return 0; 605} 606 607static int vega20_ih_hw_fini(void *handle) 608{ 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610 611 vega20_ih_irq_disable(adev); 612 613 return 0; 614} 615 616static int vega20_ih_suspend(void *handle) 617{ 618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 619 620 return vega20_ih_hw_fini(adev); 621} 622 623static int vega20_ih_resume(void *handle) 624{ 625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626 627 return vega20_ih_hw_init(adev); 628} 629 630static bool vega20_ih_is_idle(void *handle) 631{ 632 /* todo */ 633 return true; 634} 635 636static int vega20_ih_wait_for_idle(void *handle) 637{ 638 /* todo */ 639 return -ETIMEDOUT; 640} 641 642static int vega20_ih_soft_reset(void *handle) 643{ 644 /* todo */ 645 646 return 0; 647} 648 649static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 650 bool enable) 651{ 652 uint32_t data, def, field_val; 653 654 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 655 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 656 field_val = enable ? 0 : 1; 657 data = REG_SET_FIELD(data, IH_CLK_CTRL, 658 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 659 data = REG_SET_FIELD(data, IH_CLK_CTRL, 660 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 661 data = REG_SET_FIELD(data, IH_CLK_CTRL, 662 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 663 data = REG_SET_FIELD(data, IH_CLK_CTRL, 664 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 665 data = REG_SET_FIELD(data, IH_CLK_CTRL, 666 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 667 data = REG_SET_FIELD(data, IH_CLK_CTRL, 668 DYN_CLK_SOFT_OVERRIDE, field_val); 669 data = REG_SET_FIELD(data, IH_CLK_CTRL, 670 REG_CLK_SOFT_OVERRIDE, field_val); 671 if (def != data) 672 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 673 } 674} 675 676static int vega20_ih_set_clockgating_state(void *handle, 677 enum amd_clockgating_state state) 678{ 679 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 680 681 vega20_ih_update_clockgating_state(adev, 682 state == AMD_CG_STATE_GATE); 683 return 0; 684 685} 686 687static int vega20_ih_set_powergating_state(void *handle, 688 enum amd_powergating_state state) 689{ 690 return 0; 691} 692 693const struct amd_ip_funcs vega20_ih_ip_funcs = { 694 .name = "vega20_ih", 695 .early_init = vega20_ih_early_init, 696 .late_init = NULL, 697 .sw_init = vega20_ih_sw_init, 698 .sw_fini = vega20_ih_sw_fini, 699 .hw_init = vega20_ih_hw_init, 700 .hw_fini = vega20_ih_hw_fini, 701 .suspend = vega20_ih_suspend, 702 .resume = vega20_ih_resume, 703 .is_idle = vega20_ih_is_idle, 704 .wait_for_idle = vega20_ih_wait_for_idle, 705 .soft_reset = vega20_ih_soft_reset, 706 .set_clockgating_state = vega20_ih_set_clockgating_state, 707 .set_powergating_state = vega20_ih_set_powergating_state, 708}; 709 710static const struct amdgpu_ih_funcs vega20_ih_funcs = { 711 .get_wptr = vega20_ih_get_wptr, 712 .decode_iv = amdgpu_ih_decode_iv_helper, 713 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 714 .set_rptr = vega20_ih_set_rptr 715}; 716 717static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 718{ 719 adev->irq.ih_funcs = &vega20_ih_funcs; 720} 721 722const struct amdgpu_ip_block_version vega20_ih_ip_block = { 723 .type = AMD_IP_BLOCK_TYPE_IH, 724 .major = 4, 725 .minor = 2, 726 .rev = 0, 727 .funcs = &vega20_ih_ip_funcs, 728}; 729