#
6a7cbbc2 |
|
06-Mar-2024 |
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> |
drm/amdgpu/vcn: enable vcn1 fw load for VCN 4_0_6 v1 - update the fw header for each vcn instance (Veera) VCN1 has different FW binary in VCN v4_0_6. Add changes to load the VCN1 fw binary Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ddcdb7c |
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07-Jul-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: use psp_execute_load_ip_fw instead Replace the old ones with psp_execute_load_ip_fw. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f4caf584 |
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14-Sep-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: introduce vmhub definition for multi-partition cases (v3) v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0530553b |
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19-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4) It looks better to place this field in ring structure. Also drop the repeated ring funcs definitions if there's no difference except for vmhub field. v2: rename the field to vm_hub like others (Le) v3: apply the changes to new ip blocks (Hawking) v4: fix vcn sw ring (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69939009 |
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28-Dec-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Load VCN microcode during early_init Simplifies the code so that all VCN versions will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b857e147 |
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03-Dec-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: move out asic specific definition from common header Move out asic specific definition from common header. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3748424b |
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19-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: use ring structure to access rptr/wptr v2 Use ring structure to access the cpu/gpu address of rptr/wptr. v2: merge gfx10/sdma5/sdma5.2 patches Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e2f50e2 |
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14-Mar-2022 |
Tianci Yin <tianci.yin@amd.com> |
drm/amdgpu/vcn: fix vcn ring test failure in igt reload test [why] On Renoir, vcn ring test failed on the second time insmod in the reload test. After investigation, it proves that vcn only can disable dpg under dpg unpause mode (dpg unpause mode is default for dec only, dpg pause mode is for dec/enc). [how] unpause dpg in dpg stopping procedure. Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c0f11ff |
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14-Mar-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: only allow secure submission on rings which support that Only GFX ring, SDMA ring and VCN decode ring support secure submission at the moment. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11eb648d |
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02-Mar-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: Add vcn firmware log vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b6065ebf |
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02-Mar-2022 |
Ruijing Dong <ruijing.dong@amd.com> |
drm/amdgpu/vcn: Update fw shared data structure Add fw log in fw shared data structure. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7876c7ea |
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18-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vcn2.0: remove intermediate variable No need to use the tmp variable, just use the constant directly. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c5dd5667 |
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19-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Consolidate VCN firmware setup code Roughly the same code was present in all VCN versions. Consolidate it into a single function. v2: use AMDGPU_UCODE_ID_VCN + i, check if num_inst >= 2 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com>
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#
c58a863b |
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08-Oct-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: use adev_to_drm for consistency when accessing drm_device adev_to_drm is used everywhere, so improve recent changes when accessing drm_device pointer from amdgpu_device. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b592d00 |
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08-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vcn: remove manual instance setting Handled by IP discovery now. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c03509cb |
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15-Sep-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix MMIO access page fault Add more guards to MMIO access post device unbind/unplug Bug: https://bugs.archlinux.org/task/72092?project=1&order=dateopened&sort=desc&pagenum=1 Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ad29a4e |
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27-Aug-2021 |
Satyajit Sahu <satyajit.sahu@amd.com> |
drm/amdgpu/vcn: set the priority for each encode ring VCN has multiple rings. Set the proper priority level for each encode ring while initializing. Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
95f71f12 |
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14-Jul-2021 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Fix a printing message The printing message "PSP loading VCN firmware" is mis-leading because people might think driver is loading VCN firmware. Actually when this message is printed, driver is just preparing some VCN ucode, not loading VCN firmware yet. The actual VCN firmware loading will be in the PSP block hw_init. Fix the printing message Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
386061cd |
|
19-May-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.0: add cancel_delayed_work_sync before power gate Add cancel_delayed_work_sync before set power gating state to avoid race condition issue when power gating. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0c601337 |
|
19-May-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.0: add cancel_delayed_work_sync before power gate Add cancel_delayed_work_sync before set power gating state to avoid race condition issue when power gating. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
c107171b |
|
02-Feb-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add the sched_score to amdgpu_ring_init Allow separate ring to share the same scheduler score. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6c93cc2c |
|
24-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/amdgpu/vcn_v2_0: Fix a few kernel-doc misdemeanours Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:483: warning: Excess function parameter 'sw' description in 'vcn_v2_0_disable_clock_gating' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:644: warning: Excess function parameter 'sw' description in 'vcn_v2_0_enable_clock_gating' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1404: warning: Function parameter or member 'count' not described in 'vcn_v2_0_dec_ring_insert_nop' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1426: warning: Function parameter or member 'addr' not described in 'vcn_v2_0_dec_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1426: warning: Function parameter or member 'seq' not described in 'vcn_v2_0_dec_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1426: warning: Function parameter or member 'flags' not described in 'vcn_v2_0_dec_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1426: warning: Excess function parameter 'fence' description in 'vcn_v2_0_dec_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1465: warning: Function parameter or member 'job' not described in 'vcn_v2_0_dec_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1465: warning: Function parameter or member 'flags' not described in 'vcn_v2_0_dec_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1609: warning: Function parameter or member 'addr' not described in 'vcn_v2_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1609: warning: Function parameter or member 'seq' not described in 'vcn_v2_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1609: warning: Function parameter or member 'flags' not described in 'vcn_v2_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1609: warning: Excess function parameter 'fence' description in 'vcn_v2_0_enc_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1636: warning: Function parameter or member 'job' not described in 'vcn_v2_0_enc_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1636: warning: Function parameter or member 'flags' not described in 'vcn_v2_0_enc_ring_emit_ib' Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
715c84ff |
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02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu/vcn: use "*" adjacent to data name When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding style standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a971887e |
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02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu/vcn: improve code indentation and alignment General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f349f772 |
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22-Sep-2020 |
Bernard Zhao <bernard@vivo.com> |
drm/amd: fix typoes in comments Change the comment typo: "programm" -> "program". Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9a69574b |
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01-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use register distance member instead of hardcode in VCN2/JEPG2 This patch updates to use register distance member instead of hardcode in VCN2/JEPG2. They are for the same ASIC. Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: AnZhong Huang <anzhong.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
450da2ef |
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17-Jun-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: fix unused variable SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reported-by: kernel test robot <lkp@intel.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
617f90d9 |
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17-Jun-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.0: fix no previous prototype for functions Include header file vcn_v2_0.h Signed-off-by: James Zhu <James.Zhu@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4d319ed6 |
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30-Mar-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0 Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0. These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename it to be a general name. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b3583347 |
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29-Apr-2020 |
Zheng Bin <zhengbin13@huawei.com> |
drm/amdgpu: remove set but not used variable 'direct_poll' in vcn_v2_0.c Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1848:39: warning: variable ‘direct_poll’ set but not used [-Wunused-but-set-variable] It is introduced by commit dd26858a9cd8 ("drm/amdgpu: implement initialization part on VCN2.0 for SRIOV"), but never used, so remove it. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c6d567b |
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01-Apr-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: rework sched_list generation Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
93521410 |
|
29-Mar-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.0: Add firmware w/r ptr reset sync Add firmware write/read point reset sync through shared memory Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ef563ff4 |
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18-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR reset Add vcn dpg harware synchronization to fix race condition issue between vcn driver and hardware. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1675c3a2 |
|
21-Feb-2020 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: stop disable the scheduler during HW fini When we stop the HW for example for GPU reset we should not stop the front-end scheduler. Otherwise we run into intermediate failures during command submission. The scheduler should only be stopped in very few cases: 1. We can't get the hardware working in ring or IB test after a GPU reset. 2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset. 3. In amdgpu_ring_fini() when the driver unloads. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Test-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ad31da43 |
|
25-Mar-2020 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: No need support vcn decode As no need to support vcn decode feature, so disable the ring for SR-IOV. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
23edf7f1 |
|
18-Mar-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: fix typo for vcn2/jpeg2 idle check fix typo for vcn2/jpeg2 idle check Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b5689d22 |
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18-Mar-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: fix typo for vcn2/jpeg2 idle check fix typo for vcn2/jpeg2 idle check Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cc9f2fba |
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05-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: disable clock/power gating for SRIOV and disable MC resum in VCN2.0 as well those are not concerned by VF driver Singed-off-by: darlington Opara <darlington.opara@amd.com> Signed-off-by: Jinage Zhao <jiange.zhao@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
68430c6b |
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05-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0 (v2) support IB test on dec/enc ring disable ring test on dec/enc ring (MMSCH limitation) v2: squash in unused variable warning fix Singed-off-by: darlington Opara <darlington.opara@amd.com> Signed-off-by: Jinage Zhao <jiange.zhao@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dd26858a |
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05-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: implement initialization part on VCN2.0 for SRIOV something need to do for VCN2.0 enablement on SRIOV: 1)use one dec ring and one enc ring 2)allocate MM table for MMSCH usage 3)implement SRIOV version vcn_start which orgnize vcn programing with patcket format and implement start mmsch for to run those packet 4)doorbell is changed for SRIOV Singed-off-by: darlington Opara <darlington.opara@amd.com> Signed-off-by: Jinage Zhao <jiange.zhao@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f4d0242b |
|
05-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1 Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
80ff3e10 |
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05-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1 Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b6501217 |
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20-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 Share vcn_v2_0_dec_ring_test_ring to vcn2.5 to support vcn software ring. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a9d4fe2f |
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20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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45cec87c |
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15-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: move macro from vcn2.0 to share amdgpu_vcn (v2) Move macro from vcn2.0 to amdgpu_vcn to share with vcn2.5 v2: squash in macro fix Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5db86843 |
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15-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: support multiple instance direct SRAM read and write (v2) Add multiple instance direct SRAM read and write support for vcn2.5 v2: squash in indexing fix Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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597e6ac3 |
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13-Jan-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: support multiple-instance dpg pause mode Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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21a174f5 |
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08-Dec-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: fix VCN2.x number of irq types The JPEG irq type has been moved to its own structure Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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14f43e8f |
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11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: move JPEG2.5 out from VCN2.5 And clean up the duplicated stuff Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b0f3cd31 |
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08-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0 They are no longer needed, using from JPEG2.0 instead. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fd287c8c |
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01-Oct-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/vcn: use amdgpu_ring_test_helper Instead of amdgpu_ring_test_ring, so the helper function determines whether the ring is ready Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Cc: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bebc0762 |
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23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure no functional change, just switch to new structures Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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134b1461 |
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22-Aug-2019 |
Thong Thai <thong.thai@amd.com> |
Revert "drm/amdgpu: use direct loading on renoir vcn for the moment" This reverts commit 444a0fea5107e9ad7e3cbbafed78678489e31713. We are ready to enable it now. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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444a0fea |
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21-Jul-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use direct loading on renoir vcn for the moment PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d1836f38 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0 VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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af655cc5 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9a2ffeb5 |
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31-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop drmP.h from vcn_v2_0.c And fix the fallout. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c74dbe44 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0 VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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333fe325 |
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25-Jul-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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53ef3969 |
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18-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: use VCN firmware offset for cache window Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c01b6a1d |
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10-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: modify amdgpu_vcn to support multiple instances Arcturus has dual-VCN. Need Restruct amdgpu_device::vcn to support multiple vcns. There are no any logical changes here Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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989b6a05 |
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10-Jul-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance add vcn nbio doorbell range setting for 2nd vcn instance Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cdbd115e |
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09-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2: expose rings functions They can be reused by VCN2.x family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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22a8f442 |
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15-Apr-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2: put IB internal registers offset to structure So the ring functions can be shared with different VCN versions with different internal registers offsets Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a2d15ed7 |
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16-Jul-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c6d5245d |
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18-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: use VCN firmware offset for cache window Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d8dfc3bd |
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27-Jun-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix warning on 32 bit Properly cast pointer to int. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dc8ae677 |
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27-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN: implement indirect DPG SRAM mode SRAM will be programmed by PSP Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7282da0b |
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23-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0: add DPG pause mode Pause the DPG when not doing decode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bf4865b5 |
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14-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0: add DPG mode start and stop (v2) This is for using SRAM directly v2: rebase (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b3ef5ce0 |
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13-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0 remove unused Macro and declaration Just for cleanup Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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863dd269 |
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30-Apr-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCN2.0: remove powergating for UVDW tile No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0b8794e2 |
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18-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/vcn2: don't access register when power gated It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c113ba15 |
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18-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/vcn2: notify SMU power up/down VCN For sw control power gating, it needs notify SMU to power up/down VCN when enter/exit working state. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1b61de45 |
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15-Oct-2018 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add initial VCN2.0 support (v2) VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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