Lines Matching refs:wptr
93 ret = ring->wptr & ring->buf_mask;
123 * Get the current wptr from the hardware.
127 u64 wptr = 0;
131 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
132 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
135 return wptr >> 2;
143 * Write the wptr back to the hardware.
152 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
153 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
155 lower_32_bits(ring->wptr << 2),
156 upper_32_bits(ring->wptr << 2));
159 ring->wptr << 2);
161 ring->doorbell_index, ring->wptr << 2);
162 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
168 lower_32_bits(ring->wptr << 2),
170 upper_32_bits(ring->wptr << 2));
173 lower_32_bits(ring->wptr << 2));
176 upper_32_bits(ring->wptr << 2));
215 * wptr + 6 + x = 8k, k >= 0, which in C is,
216 * (wptr + 6 + x) % 8 = 0.
219 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
456 /* setup the wptr shadow polling */
476 ring->wptr = 0;
478 /* before programing wptr to a less value, need set minor_ptr_update first */
481 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
483 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
507 /* set minor_ptr_update to 0 after wptr programed */