amd/amdgpu/vcn_v2_0.c

919 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
921 		lower_32_bits(ring->wptr));
1077 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1079 			lower_32_bits(ring->wptr));
1084 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1085 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1093 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1094 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1237 				ring->wptr = 0;
1241 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1242 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1247 				ring->wptr = 0;
1251 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1252 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1361 			lower_32_bits(ring->wptr) | 0x80000000);
1364 		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1365 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1367 		WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1416 	WARN_ON(ring->wptr % 2 || count % 2);
1596 			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1597 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1599 			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1603 			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1604 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1606 			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1819 	adev->vcn.inst->ring_dec.wptr = 0;
1824 		adev->vcn.inst->ring_enc[i].wptr = 0;
1951 			ring->wptr = 0;
1964 		ring->wptr = 0;