#
9217b91c |
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22-Jan-2024 |
Friedrich Vock <friedrich.vock@gmx.de> |
drm/amdgpu: Reset IH OVERFLOW_CLEAR bit Allows us to detect subsequent IH ring buffer overflows as well. Cc: Joshua Ashton <joshua@froggi.es> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Friedrich Vock <friedrich.vock@gmx.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2763da27 |
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10-Jan-2024 |
chenxuebing <chenxb_99091@126.com> |
drm/amdgpu: Clean up errors in navi10_ih.c Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: chenxuebing <chenxb_99091@126.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73302562 |
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22-Jan-2024 |
Friedrich Vock <friedrich.vock@gmx.de> |
drm/amdgpu: Reset IH OVERFLOW_CLEAR bit Allows us to detect subsequent IH ring buffer overflows as well. Cc: Joshua Ashton <joshua@froggi.es> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Friedrich Vock <friedrich.vock@gmx.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e0a3e7bf |
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29-Sep-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Drop unnecessary return statements There is no reason to call return at the end of function that returns void. Fixes the below: WARNING: void function return statements are not generally useful Thus remove such a statement in the affected functions. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e8303cf |
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11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf80d34b |
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07-Jul-2023 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: Increase soft IH ring size Retry faults are delegated to soft IH ring and then processed by deferred worker. Current soft IH ring size PAGE_SIZE can store 128 entries, which may overflow and drop retry faults, causes HW stucks because the retry fault is not recovered. Increase soft IH ring size to 8KB, enough to store 256 CAM entries because we clear the CAM entry after handling the retry fault from soft ring. Define macro IH_RING_SIZE and IH_SW_RING_SIZE to remove duplicate constant. Show warning message if soft IH ring overflows with CAM enabled because this should not happen. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
de8341ee |
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12-Aug-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Fix interrupt handling on ih_soft ring There are no backing hardware registers for ih_soft ring. As a result, don't try to access hardware registers for read and write pointers when processing interrupts on the IH soft ring. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
364d453f |
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28-Apr-2022 |
Minghao Chi <chi.minghao@zte.com.cn> |
drm/amdgpu: simplify the return expression of navi10_ih_hw_init() Simplify the return expression. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25faeddc |
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25-Mar-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expand cg_flags from u32 to u64 With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3c2d6ea2 |
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18-Nov-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: handle IH ring1 overflow IH ring1 is used to process GPU retry fault, overflow is enabled to drain retry fault because we want receive other interrupts while handling retry fault to recover range. There is no overflow flag set when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow and drain retry fault. If fault timestamp goes backward, the fault is filtered and should not be processed. Drain fault is finished if processed_timestamp is equal to or larger than checkpoint timestamp. Add amdgpu_ih_functions interface decode_iv_ts for different chips to get timestamp from IV entry with different iv size and timestamp offset. amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
23eb4925 |
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23-Nov-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: enable Navi retry fault wptr overflow If xnack is on, VM retry fault interrupt send to IH ring1, and ring1 will be full quickly. IH cannot receive other interrupts, this causes deadlock if migrating buffer using sdma and waiting for sdma done while handling retry fault. Remove VMC from IH storm client, enable ring1 write pointer overflow, then IH will drop retry fault interrupts and be able to receive other interrupts while driver is handling retry fault. IH ring1 write pointer doesn't writeback to memory by IH, and ring1 write pointer recorded by self-irq is not updated, so always read the latest ring1 write pointer from register. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
71ee9236 |
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23-Nov-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: enable Navi 48-bit IH timestamp counter By default this timestamp is 32 bit counter. It gets overflowed in around 10 minutes. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4ef8a73 |
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23-Nov-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: enable Navi retry fault wptr overflow If xnack is on, VM retry fault interrupt send to IH ring1, and ring1 will be full quickly. IH cannot receive other interrupts, this causes deadlock if migrating buffer using sdma and waiting for sdma done while handling retry fault. Remove VMC from IH storm client, enable ring1 write pointer overflow, then IH will drop retry fault interrupts and be able to receive other interrupts while driver is handling retry fault. IH ring1 write pointer doesn't writeback to memory by IH, and ring1 write pointer recorded by self-irq is not updated, so always read the latest ring1 write pointer from register. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8888e2fe |
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23-Nov-2021 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: enable Navi 48-bit IH timestamp counter By default this timestamp is 32 bit counter. It gets overflowed in around 10 minutes. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d789535 |
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04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7c69d615 |
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27-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/navi10_ih: convert to IP version checking Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2b9ced5a |
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08-Jun-2021 |
Rohit Khaire <rohit.khaire@amd.com> |
drm/amdgpu: Use PSP to program IH_RB_CNTL_RING1/2 on SRIOV This is similar to IH_RB_CNTL programming in navi10_ih_toggle_ring_interrupts Signed-off-by: Rohit Khaire <rohit.khaire@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Horace Chen <horace.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f82e7e49 |
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03-Nov-2020 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add yellow carp support for ih block This patch adds the support for yellow carp ih block. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d10d0daa |
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17-May-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Handle IOMMU enabled case. Problem: Handle all DMA IOMMU group related dependencies before the group is removed. Those manifest themself in that when IOMMU enabled DMA map/unmap is dependent on the presence of IOMMU group the device belongs to but, this group is released once the device is removed from PCI topology. Fix: Expedite all such unmap operations to pci remove driver callback. v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate v6: Drop the BO unamp list v7: Drop amdgpu_gart_fini In amdgpu_ih_ring_fini do uncinditional check (!ih->ring) to avoid freeing uniniitalized rings. Call amdgpu_ih_ring_fini unconditionally. v8: Add deatiled explanation Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210517143851.475058-1-andrey.grodzovsky@amd.com
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#
72c8c97b |
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12-May-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Split amdgpu_device_fini into early and late Some of the stuff in amdgpu_device_fini such as HW interrupts disable and pending fences finilization must be done right away on pci_remove while most of the stuff which relates to finilizing and releasing driver data structures can be kept until drm_driver.release hook is called, i.e. when the last device reference is dropped. v4: Change functions prefix early->hw and late->sw Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512142648.666476-3-andrey.grodzovsky@amd.com
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#
4aa7e6e0 |
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11-May-2021 |
YuBiao Wang <YuBiao.Wang@amd.com> |
drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid [Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Reviewed-by: Chen, Horace <Horace.Chen@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a1dede36 |
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13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add ih ip block for beige_goby Enable ih block for beige_goby, same as dimgrey_cavefish Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4f1431db |
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22-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: drop psp ih programming for sriov guest on navi the psp access ih path is not needed in navi Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jane Jian <Jane.Jian@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a0a0d6d |
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20-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: de-initialize software ih ring tear down software ih ring and its state. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7f03b148 |
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20-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: set ih soft ring enabled flag for vega and navi software ih ring is enabled in vega10 and navi ih block by default. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
580a6d2f |
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08-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: retire the vega20 code path from navi10 ih block already switched to vega20 ih block for vega20 and arcturus. no need to add vega20 support in navi10 ih block Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
40838281 |
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25-Nov-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common decode iv helper The iv format is the same for all the soc15 adpater and onwards and can share a common function to decode iv. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d2fbf68 |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: use cached ih rb control reg offsets for navi10 all the ih rb control register offsets are cached at the beginning of navi10 ih_sw_init. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fc4aa19f |
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08-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to ih_enable_ring for navi10 use navi10_ih_enable_ring to enable all the available ring buffers for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6e7b7c7f |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to ih_toggle_interrupts for navi10 replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a362976b |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to ih_init_register_offset for navi10 Initialize ih control registers offset through helper function navi10_ih_init_register_offset. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ce6940e |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper to toggle ih ring interrupts for navi10 navi10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1514cb7d |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper to enable an ih ring for navi10 navi10_ih_enable_ring will be used to enable an ih ring for navi1x and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5212d163 |
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01-Dec-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper to init ih ring regs for navi10 navi10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c56fb081 |
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24-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/amdgpu/navi10_ih: Add descriptions for 'ih' and 'entry' Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/navi10_ih.c:453: warning: Function parameter or member 'ih' not described in 'navi10_ih_get_wptr' drivers/gpu/drm/amd/amdgpu/navi10_ih.c:512: warning: Function parameter or member 'ih' not described in 'navi10_ih_decode_iv' drivers/gpu/drm/amd/amdgpu/navi10_ih.c:512: warning: Function parameter or member 'entry' not described in 'navi10_ih_decode_iv' drivers/gpu/drm/amd/amdgpu/navi10_ih.c:552: warning: Function parameter or member 'ih' not described in 'navi10_ih_irq_rearm' drivers/gpu/drm/amd/amdgpu/navi10_ih.c:585: warning: Function parameter or member 'ih' not described in 'navi10_ih_set_rptr' Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Alex Sierra <alex.sierra@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d4581f7d |
|
03-Nov-2020 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: enabled software IH ring for Navi Felix pointed out that we need this for Navi as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
771cc67e |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add ih ip block for dimgrey_cavefish Enable ih block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf13cb1f |
|
08-Jul-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh The interrupts are not stable while uses guest physical address (GPA) for interrupt packet write space even on direct loading case. v2: make condition more readable Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd4f2811 |
|
27-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add van gogh support for ih block This patch adds the support for van gogh ih block. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
abb6fccb |
|
01-Sep-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: enable ih1 ih2 for Arcturus only Enable multi-ring ih1 and ih2 for Arcturus only. For Navi10 family multi-ring has been disabled. Apparently, having multi-ring enabled in Navi was causing continus page fault interrupts. Further investigation is needed to get to the root cause. Related issue link: https://gitlab.freedesktop.org/drm/amd/-/issues/1279 Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5ea6f9c2 |
|
14-Jul-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2) outstanding log reaches threshold will trigger IH ring1/2's wptr reported, that will avoid generating interrupts to ring0 too frequent. But if ring1/2's wptr hasn't been increased for a long time, the outstanding log can't reach threshold so that driver can't get latest wptr info and miss some interrupts. v2: squash in warning fix Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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026c396b |
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12-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add ih ip block for navy_flounder navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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757b3af8 |
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16-Jun-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add ih ip block for sienna_cichlid Update IH handling for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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193cce34 |
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01-Apr-2020 |
Alex Sierra <alex.sierra@amd.com> |
amdgpu/drm: remove psp access on navi10 for sriov Navi ASICs don't require to access through PSP to osssys registers. This on SR-IOV configuration. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9e94ff33 |
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23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5 [Why] Due Page faults can easily overwhelm the interrupt handler. So to make sure that we never lose valuable interrupts on the primary ring we re-route page faults to IH ring 1. It also facilitates the recovery page process, since it's already running from a process context. This is valid for Arcturus and future Navi generation GPUs. [How] Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0ab176e6 |
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23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ab518012 |
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23-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: enable IH ring 1 and ring 2 for navi Support added into IH to enable ring1 and ring2 for navi10_ih. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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022b6518 |
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05-Feb-2020 |
Samir Dhume <samir.dhume@amd.com> |
drm/amdgpu: Rearm IRQ in Navi10 SR-IOV if IRQ lost Ported from Vega10. SDMA stress tests sometimes see IRQ lost. Signed-off-by: Samir Dhume <samir.dhume@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a9d4fe2f |
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20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7eca4006 |
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20-Dec-2019 |
Ma Feng <mafeng.ma@huawei.com> |
drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.c Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/navi10_ih.c:113:5-8: Unneeded variable: "ret". Return "0" on line 182 Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ma Feng <mafeng.ma@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bebc0762 |
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23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure no functional change, just switch to new structures Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b23b2e9e |
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31-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop drmP.h from navi10_ih.c And fix the fallout. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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edc61147 |
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02-Mar-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add navi10 ih ip block (v3) IH is the interrupt handler block. v1: add initial ih support (Ray) v2: add dummy prescreen iv function for navi10 (Hawking) v3: squash in additional updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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