Searched refs:levels (Results 26 - 50 of 116) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c954 /* populate graphics levels */
1014 struct SMU73_Discrete_GraphicsLevel *levels = local
1025 &levels[i]);
1031 levels[i].DeepSleepDivId = 0;
1035 levels[0].EnabledForActivity = 1;
1038 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1048 "There must be 1 or more PCIE levels defined in PPTable.",
1052 levels[i].pcieDpmLevel =
1077 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1080 levels[
1230 struct SMU73_Discrete_MemoryLevel *levels = local
2555 struct SMU73_Discrete_GraphicsLevel *levels = local
[all...]
H A Dvegam_smumgr.c407 /* Setup BIF_SCLK levels */
822 /* populate graphics levels */
878 struct SMU75_Discrete_GraphicsLevel *levels = local
896 levels[i].UpHyst = (uint8_t)
898 levels[i].DownHyst = (uint8_t)
902 levels[i].DeepSleepDivId = 0;
914 levels[i].EnabledForActivity =
919 "There must be 1 or more PCIE levels defined in PPTable.",
923 levels[i].pcieDpmLevel =
948 levels[
1045 struct SMU75_Discrete_MemoryLevel *levels = local
[all...]
/linux-master/fs/qnx6/
H A Dinode.c216 pr_debug("inode_levels: %02x\n", sb->Inode.levels);
416 /* sanity check - limit maximum indirect pointer levels */
417 if (sb1->Inode.levels > QNX6_PTR_MAX_LEVELS) {
418 pr_err("too many inode levels (max %i, sb %i)\n",
419 QNX6_PTR_MAX_LEVELS, sb1->Inode.levels);
422 if (sb1->Longfile.levels > QNX6_PTR_MAX_LEVELS) {
423 pr_err("too many longfilename levels (max %i, sb %i)\n",
424 QNX6_PTR_MAX_LEVELS, sb1->Longfile.levels);
511 ei->di_filelevels = p->levels;
/linux-master/drivers/rtc/
H A Drtc-isl12022.c292 u32 levels[2] = {0, 0}; local
296 device_property_read_u32_array(dev, "isil,battery-trip-levels-microvolt",
297 levels, 2);
301 if (levels[i] <= trip_levels[i][j])
313 dev_warn(dev, "unable to set battery alarm levels: %d\n", ret);
/linux-master/include/linux/
H A Dqnx6_fs.h29 #define QNX6_PTR_MAX_LEVELS 5 /* maximum indirect levels */
89 __u8 levels; member in struct:qnx6_root_node
/linux-master/drivers/md/persistent-data/
H A Ddm-btree.h88 unsigned int levels; member in struct:dm_btree_info
/linux-master/arch/x86/kernel/cpu/microcode/
H A Dcore.c69 * Those patch levels cannot be updated to newer ones and thus should be final.
90 u32 *levels; local
94 levels = final_levels;
96 for (i = 0; levels[i]; i++) {
97 if (lvl == levels[i])
/linux-master/drivers/md/
H A Ddm-verity.h54 unsigned char levels; /* the number of tree levels */ member in struct:dm_verity
H A Ddm-verity-target.c378 if (likely(v->levels)) {
393 for (i = v->levels - 1; i >= 0; i--) {
756 for (i = v->levels - 2; i >= 0; i--) {
1440 v->levels = 0;
1442 while (v->hash_per_block_bits * v->levels < 64 &&
1444 (v->hash_per_block_bits * v->levels))
1445 v->levels++;
1447 if (v->levels > DM_VERITY_MAX_LEVELS) {
1448 ti->error = "Too many tree levels";
1454 for (i = v->levels
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/linux-master/drivers/base/
H A Dcacheinfo.c44 * system-wide shared caches for all other levels.
191 * overriding the architecturally specified levels, so
292 unsigned int levels = 0, leaves, level; local
301 levels = 1;
311 if (level <= levels)
315 levels = level;
319 this_cpu_ci->num_levels = levels;
497 unsigned int levels = 0, split_levels = 0; local
503 ret = acpi_get_cache_info(cpu, &levels, &split_levels);
505 this_cpu_ci->num_levels = levels;
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.h49 struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; member in struct:trinity_ps
H A Dkv_dpm.h82 struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; member in struct:kv_ps
H A Dsumo_dpm.h46 struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; member in struct:sumo_ps
H A Drv770_smc.h128 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member in struct:RV770_SMC_SWSTATE
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.c377 /* Here use 4 levels, make sure not exceed */
1355 return smu8_ps->levels[0].engineClock;
1357 return smu8_ps->levels[smu8_ps->level-1].engineClock;
1369 smu8_ps->levels[0] = data->boot_power_level;
1391 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1392 smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1397 smu8_ps->levels[index].dsDividerIndex = 5;
1398 smu8_ps->levels[index].ssDividerIndex = 5;
1612 level->coreClock = ps->levels[level_index].engineClock;
1616 if (ps->levels[
[all...]
H A Dsmu10_hwmgr.c897 smu10_ps->levels[index].engine_clock = 0;
899 smu10_ps->levels[index].vddc_index = 0;
903 smu10_ps->levels[index].ds_divider_index = 5;
904 smu10_ps->levels[index].ss_divider_index = 5;
986 pr_info("Currently sclk only support 3 levels on RV\n");
1137 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1138 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
/linux-master/arch/sparc/kernel/
H A Dsun4d_smp.c225 * | bcast | devid | sid | levels mask |
229 #define IGEN_MESSAGE(bcast, devid, sid, levels) \
230 (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
/linux-master/arch/powerpc/platforms/powernv/
H A Dpci.h287 __u64 window_size, __u32 levels);
315 __u32 page_shift, __u64 window_size, __u32 levels,
H A Dpci-ioda.c1345 int num, __u32 page_shift, __u64 window_size, __u32 levels,
1363 levels, alloc_userspace_copy, tbl);
1406 unsigned int levels = tces_order / tcelevel_order; local
1409 levels += 1;
1411 * We try to stick to default levels (which is >1 at the moment) in
1414 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
1417 window_size, levels, false, &tbl);
1468 0/* levels */, 0/* table address */,
1482 __u64 window_size, __u32 levels)
1344 pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, int num, __u32 page_shift, __u64 window_size, __u32 levels, bool alloc_userspace_copy, struct iommu_table **ptbl) argument
1481 pnv_pci_ioda2_get_table_size(__u32 page_shift, __u64 window_size, __u32 levels) argument
1513 pnv_pci_ioda2_create_table_userspace( struct iommu_table_group *table_group, int num, __u32 page_shift, __u64 window_size, __u32 levels, struct iommu_table **ptbl) argument
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/linux-master/arch/powerpc/include/asm/
H A Diommu.h168 __u32 levels);
173 __u32 levels,
/linux-master/drivers/vfio/
H A Dvfio_iommu_spapr_tce.c447 * and if it is missing some indirect levels, then
612 __u32 levels,
618 levels);
627 page_shift, window_size, levels, ptbl);
645 __u32 page_shift, __u64 window_size, __u32 levels,
674 page_shift, window_size, levels, &tbl);
892 info.ddw.levels = table_group->max_levels;
1137 create.window_size, create.levels,
607 tce_iommu_create_table(struct tce_container *container, struct iommu_table_group *table_group, int num, __u32 page_shift, __u64 window_size, __u32 levels, struct iommu_table **ptbl) argument
644 tce_iommu_create_window(struct tce_container *container, __u32 page_shift, __u64 window_size, __u32 levels, __u64 *start_addr) argument
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.h108 struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; member in struct:kv_ps
/linux-master/drivers/platform/x86/intel/speed_select_if/
H A Disst_tpmi_core.c143 * This structure is used store offsets of SST PP levels in the register bank.
222 * @avx_levels: Number of AVX levels
314 int levels)
319 pd_info->perf_levels = devm_kcalloc(&auxdev->dev, levels,
337 for (i = 0; i < levels; ++i) {
352 int i, mask, levels; local
378 levels = 0;
381 levels = i;
384 pd_info->max_level = levels;
385 sst_add_perf_profiles(auxdev, pd_info, levels
312 sst_add_perf_profiles(struct auxiliary_device *auxdev, struct tpmi_per_power_domain_info *pd_info, int levels) argument
[all...]
/linux-master/kernel/time/
H A Dtimer.c66 * The timer wheel has LVL_DEPTH array levels. Each level provides an array of
79 * the timers into the lower array levels. The previous 'classic' timer wheel
82 * levels provide implicit batching.
103 * This results in the following granularity and range levels:
576 * - Truncation of the expiry time in the outer wheel levels
1857 int i, levels = 0; local
1866 levels++;
1874 return levels;
1897 * Search the first expiring timer in the various clock levels. Caller must
1937 * we have to look at all levels
2391 int levels; local
[all...]
/linux-master/drivers/opp/
H A Dof.c567 unsigned int levels = opp_table->supported_hw_count; local
585 if (count <= 0 || count % levels) {
591 versions = count / levels;
593 /* All levels in at least one of the versions should match */
597 for (j = 0; j < levels; j++) {
599 i * levels + j, &val);
602 __func__, i * levels + j, ret);
1428 pr_err("%s: OPP levels aren't available for %pOF\n",

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