1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __POWERNV_PCI_H
3#define __POWERNV_PCI_H
4
5#include <linux/compiler.h>		/* for __printf */
6#include <linux/iommu.h>
7#include <asm/iommu.h>
8#include <asm/msi_bitmap.h>
9
10struct pci_dn;
11
12enum pnv_phb_type {
13	PNV_PHB_IODA2,
14	PNV_PHB_NPU_OCAPI,
15};
16
17/* Precise PHB model for error management */
18enum pnv_phb_model {
19	PNV_PHB_MODEL_UNKNOWN,
20	PNV_PHB_MODEL_P7IOC,
21	PNV_PHB_MODEL_PHB3,
22};
23
24#define PNV_PCI_DIAG_BUF_SIZE	8192
25#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
26#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
27#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
28#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
29#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
30#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/
31
32/*
33 * A brief note on PNV_IODA_PE_BUS_ALL
34 *
35 * This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
36 * the Requester ID field of the PCIe request header to determine the device
37 * (and PE) that initiated a DMA. In legacy PCI individual memory read/write
38 * requests aren't tagged with the RID. To work around this the PCIe-to-PCI
39 * bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side.
40 *
41 * PCIe-to-X bridges have a similar issue even though PCI-X requests also have
42 * a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
43 * ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
44 * side of the bridge.
45 *
46 * To work around these problems we use the BUS_ALL flag since every subordinate
47 * bus of the bridge should go into the same PE.
48 */
49
50/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
51#define PNV_IODA_STOPPED_STATE	0x8000000000000000
52
53/* Data associated with a PE, including IOMMU tracking etc.. */
54struct pnv_phb;
55struct pnv_ioda_pe {
56	unsigned long		flags;
57	struct pnv_phb		*phb;
58	int			device_count;
59
60	/* A PE can be associated with a single device or an
61	 * entire bus (& children). In the former case, pdev
62	 * is populated, in the later case, pbus is.
63	 */
64#ifdef CONFIG_PCI_IOV
65	struct pci_dev          *parent_dev;
66#endif
67	struct pci_dev		*pdev;
68	struct pci_bus		*pbus;
69
70	/* Effective RID (device RID for a device PE and base bus
71	 * RID with devfn 0 for a bus PE)
72	 */
73	unsigned int		rid;
74
75	/* PE number */
76	unsigned int		pe_number;
77
78	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
79	struct iommu_table_group table_group;
80
81	/* 64-bit TCE bypass region */
82	bool			tce_bypass_enabled;
83	uint64_t		tce_bypass_base;
84
85	/*
86	 * Used to track whether we've done DMA setup for this PE or not. We
87	 * want to defer allocating TCE tables, etc until we've added a
88	 * non-bridge device to the PE.
89	 */
90	bool			dma_setup_done;
91
92	/* MSIs. MVE index is identical for 32 and 64 bit MSI
93	 * and -1 if not supported. (It's actually identical to the
94	 * PE number)
95	 */
96	int			mve_number;
97
98	/* PEs in compound case */
99	struct pnv_ioda_pe	*master;
100	struct list_head	slaves;
101
102	/* Link in list of PE#s */
103	struct list_head	list;
104};
105
106#define PNV_PHB_FLAG_EEH	(1 << 0)
107
108struct pnv_phb {
109	struct pci_controller	*hose;
110	enum pnv_phb_type	type;
111	enum pnv_phb_model	model;
112	u64			hub_id;
113	u64			opal_id;
114	int			flags;
115	void __iomem		*regs;
116	u64			regs_phys;
117	spinlock_t		lock;
118
119#ifdef CONFIG_DEBUG_FS
120	int			has_dbgfs;
121	struct dentry		*dbgfs;
122#endif
123
124	unsigned int		msi_base;
125	struct msi_bitmap	msi_bmp;
126	int (*init_m64)(struct pnv_phb *phb);
127	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
128	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
129	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
130
131	struct {
132		/* Global bridge info */
133		unsigned int		total_pe_num;
134		unsigned int		reserved_pe_idx;
135		unsigned int		root_pe_idx;
136
137		/* 32-bit MMIO window */
138		unsigned int		m32_size;
139		unsigned int		m32_segsize;
140		unsigned int		m32_pci_base;
141
142		/* 64-bit MMIO window */
143		unsigned int		m64_bar_idx;
144		unsigned long		m64_size;
145		unsigned long		m64_segsize;
146		unsigned long		m64_base;
147#define MAX_M64_BARS 64
148		unsigned long		m64_bar_alloc;
149
150		/* IO ports */
151		unsigned int		io_size;
152		unsigned int		io_segsize;
153		unsigned int		io_pci_base;
154
155		/* PE allocation */
156		struct mutex		pe_alloc_mutex;
157		unsigned long		*pe_alloc;
158		struct pnv_ioda_pe	*pe_array;
159
160		/* M32 & IO segment maps */
161		unsigned int		*m64_segmap;
162		unsigned int		*m32_segmap;
163		unsigned int		*io_segmap;
164
165		/* IRQ chip */
166		int			irq_chip_init;
167		struct irq_chip		irq_chip;
168
169		/* Sorted list of used PE's based
170		 * on the sequence of creation
171		 */
172		struct list_head	pe_list;
173		struct mutex            pe_list_mutex;
174
175		/* Reverse map of PEs, indexed by {bus, devfn} */
176		unsigned int		pe_rmap[0x10000];
177	} ioda;
178
179	/* PHB and hub diagnostics */
180	unsigned int		diag_data_size;
181	u8			*diag_data;
182};
183
184
185/* IODA PE management */
186
187static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
188{
189	/*
190	 * WARNING: We cannot rely on the resource flags. The Linux PCI
191	 * allocation code sometimes decides to put a 64-bit prefetchable
192	 * BAR in the 32-bit window, so we have to compare the addresses.
193	 *
194	 * For simplicity we only test resource start.
195	 */
196	return (r->start >= phb->ioda.m64_base &&
197		r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
198}
199
200static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
201{
202	unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
203
204	return (resource_flags & flags) == flags;
205}
206
207int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
208int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
209
210void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
211void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);
212
213struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count);
214void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);
215
216#ifdef CONFIG_PCI_IOV
217/*
218 * For SR-IOV we want to put each VF's MMIO resource in to a separate PE.
219 * This requires a bit of acrobatics with the MMIO -> PE configuration
220 * and this structure is used to keep track of it all.
221 */
222struct pnv_iov_data {
223	/* number of VFs enabled */
224	u16     num_vfs;
225
226	/* pointer to the array of VF PEs. num_vfs long*/
227	struct pnv_ioda_pe *vf_pe_arr;
228
229	/* Did we map the VF BAR with single-PE IODA BARs? */
230	bool    m64_single_mode[PCI_SRIOV_NUM_BARS];
231
232	/*
233	 * True if we're using any segmented windows. In that case we need
234	 * shift the start of the IOV resource the segment corresponding to
235	 * the allocated PE.
236	 */
237	bool    need_shift;
238
239	/*
240	 * Bit mask used to track which m64 windows are used to map the
241	 * SR-IOV BARs for this device.
242	 */
243	DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS);
244
245	/*
246	 * If we map the SR-IOV BARs with a segmented window then
247	 * parts of that window will be "claimed" by other PEs.
248	 *
249	 * "holes" here is used to reserve the leading portion
250	 * of the window that is used by other (non VF) PEs.
251	 */
252	struct resource holes[PCI_SRIOV_NUM_BARS];
253};
254
255static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev)
256{
257	return pdev->dev.archdata.iov_data;
258}
259
260void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev);
261resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno);
262
263int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
264int pnv_pcibios_sriov_disable(struct pci_dev *pdev);
265#endif /* CONFIG_PCI_IOV */
266
267extern struct pci_ops pnv_pci_ops;
268
269void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
270				unsigned char *log_buff);
271int pnv_pci_cfg_read(struct pci_dn *pdn,
272		     int where, int size, u32 *val);
273int pnv_pci_cfg_write(struct pci_dn *pdn,
274		      int where, int size, u32 val);
275extern struct iommu_table *pnv_pci_table_alloc(int nid);
276
277extern void pnv_pci_init_ioda_hub(struct device_node *np);
278extern void pnv_pci_init_ioda2_phb(struct device_node *np);
279extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
280extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
281extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
282
283extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);
284extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
285extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
286extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
287		__u64 window_size, __u32 levels);
288extern int pnv_eeh_post_init(void);
289
290__printf(3, 4)
291extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
292			    const char *fmt, ...);
293#define pe_err(pe, fmt, ...)					\
294	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
295#define pe_warn(pe, fmt, ...)					\
296	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
297#define pe_info(pe, fmt, ...)					\
298	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
299
300/* pci-ioda-tce.c */
301#define POWERNV_IOMMU_DEFAULT_LEVELS	2
302#define POWERNV_IOMMU_MAX_LEVELS	5
303
304extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
305		unsigned long uaddr, enum dma_data_direction direction,
306		unsigned long attrs);
307extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
308extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
309		unsigned long *hpa, enum dma_data_direction *direction);
310extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
311		bool alloc);
312extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
313
314extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
315		__u32 page_shift, __u64 window_size, __u32 levels,
316		bool alloc_userspace_copy, struct iommu_table *tbl);
317extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
318
319extern long pnv_pci_link_table_and_group(int node, int num,
320		struct iommu_table *tbl,
321		struct iommu_table_group *table_group);
322extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
323		struct iommu_table_group *table_group);
324extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
325		void *tce_mem, u64 tce_size,
326		u64 dma_offset, unsigned int page_shift);
327
328extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
329
330static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus)
331{
332	struct pci_controller *hose = bus->sysdata;
333
334	if (hose)
335		return hose->private_data;
336
337	return NULL;
338}
339
340#endif /* __POWERNV_PCI_H */
341