Lines Matching refs:levels
377 /* Here use 4 levels, make sure not exceed */
1355 return smu8_ps->levels[0].engineClock;
1357 return smu8_ps->levels[smu8_ps->level-1].engineClock;
1369 smu8_ps->levels[0] = data->boot_power_level;
1391 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1392 smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1397 smu8_ps->levels[index].dsDividerIndex = 5;
1398 smu8_ps->levels[index].ssDividerIndex = 5;
1612 level->coreClock = ps->levels[level_index].engineClock;
1616 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1617 level->coreClock = ps->levels[i].engineClock;
1628 level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1640 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1641 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));