Searched refs:block (Results 226 - 250 of 1031) sorted by last modified time

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/linux-master/drivers/hwmon/pmbus/
H A Dpmbus_core.c2449 data.block[0] = 2;
2450 data.block[1] = attr->reg;
2451 data.block[2] = 0x01;
2460 if (data.block[0] != 5)
2463 m = data.block[1] | (data.block[2] << 8);
2464 b = data.block[3] | (data.block[4] << 8);
2465 R = data.block[5];
/linux-master/drivers/gpu/drm/radeon/
H A Dsi.c4807 char *block; local
4819 block = "CB";
4829 block = "CB_FMASK";
4839 block = "CB_CMASK";
4849 block = "CB_IMMED";
4859 block = "DB";
4869 block = "DB_HTILE";
4879 block = "DB_STEN";
4893 block = "TC";
4897 block
5597 si_update_cg(struct radeon_device *rdev, u32 block, bool enable) argument
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H A Dradeon_audio.h32 #define RREG32_ENDPOINT(block, reg) \
33 radeon_audio_endpoint_rreg(rdev, (block), (reg))
34 #define WREG32_ENDPOINT(block, reg, v) \
35 radeon_audio_endpoint_wreg(rdev, (block), (reg), (v))
H A Dradeon.h186 /* CG block flags */
772 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
H A Dni.c2511 char *block; local
2522 block = "CB";
2532 block = "CB_FMASK";
2542 block = "CB_CMASK";
2552 block = "CB_IMMED";
2562 block = "DB";
2572 block = "DB_HTILE";
2582 block = "SX";
2592 block = "DB_STEN";
2602 block
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H A Dkv_dpm.c65 u32 block, bool enable);
H A Dcik.c3020 * @sh_num: sh block to address
5657 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, local
5668 block, mc_client, mc_id);
6279 u32 block, bool enable)
6282 if (block & RADEON_CG_BLOCK_GFX) {
6295 if (block & RADEON_CG_BLOCK_MC) {
6302 if (block & RADEON_CG_BLOCK_SDMA) {
6307 if (block & RADEON_CG_BLOCK_BIF) {
6311 if (block & RADEON_CG_BLOCK_UVD) {
6316 if (block
6278 cik_update_cg(struct radeon_device *rdev, u32 block, bool enable) argument
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/linux-master/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.h519 struct adreno_smmu_fault_info *info, const char *block,
597 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
/linux-master/drivers/gpu/drm/i915/selftests/
H A Dintel_memory_region.c200 /* XXX: maybe sanity check the block range here? */
306 * the max contiguous block size is SZ_64K.
344 * contiguous block. Make sure that holds true.
458 struct drm_buddy_block *block; local
497 list_for_each_entry(block, blocks, link) {
498 if (drm_buddy_block_size(mm, block) > size)
499 size = drm_buddy_block_size(mm, block);
502 pr_err("%s: Failed to create a huge contiguous block [> %u], largest block %lld\n",
539 struct drm_buddy_block *block; local
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/linux-master/drivers/gpu/drm/
H A Ddrm_edid.c1578 /*** DDC fetch and block validation ***/
1630 /* EDID block count indicated in EDID, may exceed allocated size */
1654 /* EDID block count, limited by allocated size */
1662 /* EDID extension block count, limited by allocated size */
1698 * EDID base and extension block iterator.
1701 * const u8 *block;
1704 * drm_edid_iter_for_each(block, &iter) {
1705 * // do stuff with block
1712 /* Current block index. */
1726 const void *block local
1783 const u8 *block = _block; local
1797 const struct edid *block = _block; local
1804 const u8 *block = _block; local
1860 const struct edid *block = _block; local
1901 edid_block_valid(const void *block, bool base) argument
1907 edid_block_status_print(enum edid_block_status status, const struct edid *block, int block_num) argument
1954 edid_block_dump(const char *level, const void *block, int block_num) argument
1986 struct edid *block = (struct edid *)_block; local
2047 void *block = (void *)edid_block_data(edid, i); local
2077 const void *block = drm_edid_block_data(drm_edid, i); local
2140 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) argument
2330 edid_block_read(void *block, unsigned int block_num, read_block_fn read_block, void *context) argument
2419 void *block = (void *)edid_block_data(edid, i); local
4151 const struct displayid_block *block; local
5046 const struct displayid_block *block; local
6397 drm_parse_vesa_mso_data(struct drm_connector *connector, const struct displayid_block *block) argument
6460 const struct displayid_block *block; local
6516 const struct displayid_block *block; local
6696 add_displayid_detailed_1_modes(struct drm_connector *connector, const struct displayid_block *block) argument
6726 const struct displayid_block *block; local
7269 drm_parse_tiled_block(struct drm_connector *connector, const struct displayid_block *block) argument
7324 displayid_is_tiled_block(const struct displayid_iter *iter, const struct displayid_block *block) argument
7336 const struct displayid_block *block; local
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/linux-master/drivers/gpu/drm/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.c68 static int stdp2690_read_block(void *context, u8 *buf, unsigned int block, size_t len) argument
72 unsigned char start = block * EDID_LENGTH;
H A Dlontium-lt9611.c657 lt9611_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) argument
665 /* supports up to 1 extension block */
667 if (block > 1)
670 if (block == 0) {
678 block %= 2;
679 memcpy(buf, lt9611->edid_buf + (block * 128), len);
H A Dite-it66121.c518 unsigned int block, size_t len)
525 offset = (block % 2) * len;
526 block = block / 2;
549 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
517 it66121_get_edid_block(void *context, u8 *buf, unsigned int block, size_t len) argument
H A Dite-it6505.c1140 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block, argument
1149 DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1153 block * EDID_LENGTH + offset,
/linux-master/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c415 unsigned int block, size_t length)
424 msg[0] = block / 2;
425 msg[1] = block % 2;
446 if (reg[0] == length && reg[1] == block / 2)
453 dev_err(mhdp->dev, "get block[%d] edid failed: %d\n",
454 block, ret);
414 cdns_mhdp_get_edid_block(void *data, u8 *edid, unsigned int block, size_t length) argument
/linux-master/drivers/gpu/drm/bridge/adv7511/
H A Dadv7511_drv.c536 static int adv7511_get_edid_block(void *data, u8 *buf, unsigned int block, argument
548 if (adv7511->current_edid_segment != block / 2) {
559 block);
592 adv7511->current_edid_segment = block / 2;
595 if (block % 2 == 0)
/linux-master/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h307 #define PP_CG_MSG_ID(group, block, support, state) \
308 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c141 #define SRI(reg_name, block, id)\
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
145 #define SRI_ARR(reg_name, block, id)\
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
152 #define SRI_ARR_I2C(reg_name, block, id)\
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
156 #define SRI_ARR_ALPHABET(reg_name, block, inde
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c133 #define SRI(reg_name, block, id)\
134 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
137 #define SRI2(reg_name, block, id)\
141 #define SRIR(var_name, reg_name, block, id)\
142 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
145 #define SRII(reg_name, block, id)\
146 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## i
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\
129 #define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
133 #define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## i
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c205 #define SRI(reg_name, block, id)\
206 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
207 mm ## block ## id ## _ ## reg_name
213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
214 .enable_reg = SRI(reg1, block, reg_num),\
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
221 .ack_reg = SRI(reg2, block, reg_num),\
223 block ## reg_nu
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c178 #define SRI(reg_name, block, id)\
179 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 reg ## block ## id ## _ ## reg_name
186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\
187 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
194 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
196 block ## reg_nu
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c198 #define SRI(reg_name, block, id)\
199 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 mm ## block ## id ## _ ## reg_name
203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI(reg1, block, reg_num),\
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
211 .ack_reg = SRI(reg2, block, reg_num),\
213 block ## reg_nu
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr_internal.h84 #define CLK_SRI(reg_name, block, inst)\
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 mm ## block ## _ ## inst ## _ ## reg_name
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.c1280 * to CP ip block init and ring test. IH already
1305 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {

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