Lines Matching refs:block

141 #define SRI(reg_name, block, id)\
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
145 #define SRI_ARR(reg_name, block, id)\
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
152 #define SRI_ARR_I2C(reg_name, block, id)\
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
156 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
160 #define SRI2(reg_name, block, id)\
164 #define SRI2_ARR(reg_name, block, id)\
168 #define SRIR(var_name, reg_name, block, id)\
169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
172 #define SRII(reg_name, block, id)\
173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
176 #define SRII_ARR_2(reg_name, block, id, inst)\
177 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## reg_name
180 #define SRII_MPC_RMU(reg_name, block, id)\
181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## reg_name
184 #define SRII_DWB(reg_name, temp_name, block, id)\
185 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
186 reg ## block ## id ## _ ## temp_name
188 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
191 #define DCCG_SRII(reg_name, block, id)\
192 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
193 reg ## block ## id ## _ ## reg_name
195 #define VUPDATE_SRII(reg_name, block, id)\
196 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
197 reg ## reg_name ## _ ## block ## id
1272 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1320 /* Mapping of VPG register blocks to HPO DP block instance:
1328 /* Mapping of APG register blocks to HPO DP block instance:
1336 /* allocate HPO stream encoder and create VPG sub-block */