Lines Matching refs:block
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\
129 #define SRIR(var_name, reg_name, block, id)\
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 mm ## block ## id ## _ ## reg_name
133 #define SRII(reg_name, block, id)\
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 mm ## block ## id ## _ ## reg_name
137 #define SRII_MPC_RMU(reg_name, block, id)\
138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 mm ## block ## id ## _ ## reg_name
141 #define SRII_DWB(reg_name, temp_name, block, id)\
142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
143 mm ## block ## id ## _ ## temp_name
145 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
148 #define DCCG_SRII(reg_name, block, id)\
149 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 mm ## block ## id ## _ ## reg_name
152 #define VUPDATE_SRII(reg_name, block, id)\
153 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
154 mm ## reg_name ## _ ## block ## id
185 #define CLK_SRI(reg_name, block, inst)\
186 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
187 mm ## block ## _ ## inst ## _ ## reg_name
1021 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */