#
63fcd306 |
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22-Feb-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: Enable gpu reset for S3 abort cases on Raven series Currently, GPU resets can now be performed successfully on the Raven series. While GPU reset is required for the S3 suspend abort case. So now can enable gpu reset for S3 abort cases on the Raven series. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5fe4a8d3 |
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16-Feb-2024 |
Asad Kamal <asad.kamal@amd.com> |
drm/amdgpu: Remove pcie bw sys entry Remove pcie bw sys entry for asics not supporting such function Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
86a08f1a |
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16-Feb-2024 |
Asad Kamal <asad.kamal@amd.com> |
Revert "drm/amdgpu: Add pci usage to nbio v7.9" Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c070156 |
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13-Feb-2024 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Do not toggle bif ras irq from guest Only do this from host side. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3f719cf2 |
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16-Jan-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: reset gpu for s3 suspend abort case In the s3 suspend abort case some type of gfx9 power rail not turn off from FCH side and this will put the GPU in an unknown power status, so let's reset the gpu to a known good power state before reinitialize gpu device. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c671ec01 |
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22-Feb-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: Enable gpu reset for S3 abort cases on Raven series Currently, GPU resets can now be performed successfully on the Raven series. While GPU reset is required for the S3 suspend abort case. So now can enable gpu reset for S3 abort cases on the Raven series. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ef82ac6 |
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16-Jan-2024 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: reset gpu for s3 suspend abort case In the s3 suspend abort case some type of gfx9 power rail not turn off from FCH side and this will put the GPU in an unknown power status, so let's reset the gpu to a known good power state before reinitialize gpu device. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b12fb295 |
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30-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Avoid querying DRM MGCG status MP0 v13.0.6 SOCs don't support DRM MGCG. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6146081d |
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28-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add NULL checks for function pointers Check if function is implemented before making the call. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
36fd9969 |
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28-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use another offset for GC 9.4.3 remap The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
081a6eda |
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06-Oct-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Read aquavanjaram PCIE register state Add support to read aqua vanjaram PCIE register state Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
27b024a8 |
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30-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Avoid querying DRM MGCG status MP0 v13.0.6 SOCs don't support DRM MGCG. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
81577503 |
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28-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add NULL checks for function pointers Check if function is implemented before making the call. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ed6e4f0a |
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28-Nov-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use another offset for GC 9.4.3 remap The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a6513de |
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23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move AMD_IS_APU check for ASPM into top level function There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e8303cf |
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11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6b7d2117 |
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05-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix refclk reporting for SMU v13.0.6 SMU v13.0.6 SOCs have 100MHz reference clock. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a76b2870 |
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16-May-2023 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functions Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4b9dc53 |
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19-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add SMU v13.0.6 default reset methods For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Tested-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05347402 |
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19-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add SMU v13.0.6 default reset methods For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Tested-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
59070fd9 |
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28-Jul-2023 |
Asad Kamal <asad.kamal@amd.com> |
drm/amdgpu: Add pci usage to nbio v7.9 Add implementation to get pcie usage for nbio v7.9. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50709d18 |
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27-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add pci replay count to nbio v7.9 Add implementation to get pcie replay count for nbio v7.9. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a15a77c8 |
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02-Jun-2023 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: change the reference clock for raven/raven2" This reverts commit fbc24293ca16b3b9ef891fe32ccd04735a6f8dc1. This results in inconsistent timing reported via asynchronous GPU queries. Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html Cc: Jesse.Zhang@amd.com Cc: michel@daenzer.net Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20a29ac0 |
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19-May-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: retire set_vga_state for some ASIC set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
01ef4747 |
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02-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add FGCG for GFX v9.4.3 It's not fine grain, behaves similar to MGCG. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8f2ccaaa |
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09-Mar-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add mode-2 reset in SMU v13.0.6 Modifications to mode-2 reset flow for SMU v13.0.6 ASICs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9faf929f |
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07-Feb-2023 |
Asad kamal <asad.kamal@amd.com> |
drm/amdgpu: Enable CG for IH v4.4.2 Enable clock gating on IH v4.4.2 versions. Signed-off-by: Asad kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cbf9e46a |
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03-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Enable MGCG on SDMAv4.4.2 Enable clock gating on SDMAv4.4.2 versions. Leave memory light sleep to default. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7b08b2e1 |
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31-Jan-2023 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: add vcn_4_0_3 codec query Add support for vcn_4_0_3 video codec query Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7c7011e |
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19-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Enable CGCG/LS for GC 9.4.3 Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
57a83b2d |
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23-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init gfx_v9_4_3 external_rev_id it is used for user space driver to identify gfx_v9_4_3 chip Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2fa480d3 |
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27-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add helpers to access registers on different AIDs SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs. v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1dfcdc30 |
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24-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init New doorbell index assignment is used by aqua_vanjaram. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0c552ed3 |
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02-Apr-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access nonAID0 register smn address and new PCI_INDEX_HI register is introduced to access the higher bits. v2: rebase on latest register accessors (Alex) Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
31c0ec84 |
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09-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: enable vcn DPG mode for VCN4_0_3 Enable vcn DPG mode for VCN4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ef3aa0b4 |
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09-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: enable vcn pg for VCN4_0_3 Enable vcn pg for VCN4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
342397db |
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09-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: enable vcn cg for VCN4_0_3 Enable vcn cg for VCN4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7179fc2 |
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09-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/jpeg: enable jpeg pg for VCN4_0_3 Enable jpeg pg for VCN4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
380302f8 |
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09-Jan-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/jpeg: enable jpeg cg for VCN4_0_3 Enable jpeg cg for VCN4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c312e81 |
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25-Apr-2023 |
Shane Xiao <shane.xiao@amd.com> |
drm/amdgpu: Enable doorbell selfring after resize FB BAR [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Tested-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Christian K�nig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b3ffd72 |
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02-Jun-2023 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: change the reference clock for raven/raven2" This reverts commit fbc24293ca16b3b9ef891fe32ccd04735a6f8dc1. This results in inconsistent timing reported via asynchronous GPU queries. Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html Cc: Jesse.Zhang@amd.com Cc: michel@daenzer.net Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b03f38b9 |
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25-Apr-2023 |
Shane Xiao <shane.xiao@amd.com> |
drm/amdgpu: Enable doorbell selfring after resize FB BAR [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Tested-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Christian K�nig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d51ac6d0 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5aa998ba |
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17-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to soc15_grbm_select To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6a929fea |
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26-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add common early init support for GC 9.4.3 init asic funcs and cp/pg flags for GC 9.4.3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fbc24293 |
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12-Apr-2023 |
Jesse Zhang <jesse.zhang@amd.com> |
drm/amdgpu: change the reference clock for raven/raven2 Due to switch to golden tsc register to get clock counter for raven/ raven2. Chang the reference clock from 25MHZ to 100MHZ. Suggested-by: shanshengwang <shansheng.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4489f0fd |
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06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Retire pcie_gen3_enable function Not needed since from vi. drop the function so we don't duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dabc114e |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common helper to query soc rev_id Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
65ba96e9 |
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06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common indirect reg access helper Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f651a7b6 |
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06-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15 Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0dcdf849 |
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06-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15 Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
65009bf2 |
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23-Nov-2022 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c: Corrected typo in the video capabilities resolution Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6c16afdc |
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19-Oct-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix sdma doorbell init ordering on APUs Commit 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") uncovered a bug in amdgpu that required a reordering of the driver init sequence to avoid accessing a special register on the GPU before it was properly set up leading to an PCI AER error. This reordering uncovered a different hw programming ordering dependency in some APUs where the SDMA doorbells need to be programmed before the GFX doorbells. To fix this, move the SDMA doorbell programming back into the soc15 common code, but use the actual doorbell range values directly rather than the values stored in the ring structure since those will not be initialized at this point. This is a partial revert, but with the doorbell assignment fixed so the proper doorbell index is set before it's used. Fixes: e3163bc8ffdfdb ("drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega") Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: skhan@linuxfoundation.org
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#
50b0e4d4 |
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19-Oct-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix sdma doorbell init ordering on APUs Commit 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") uncovered a bug in amdgpu that required a reordering of the driver init sequence to avoid accessing a special register on the GPU before it was properly set up leading to an PCI AER error. This reordering uncovered a different hw programming ordering dependency in some APUs where the SDMA doorbells need to be programmed before the GFX doorbells. To fix this, move the SDMA doorbell programming back into the soc15 common code, but use the actual doorbell range values directly rather than the values stored in the ring structure since those will not be initialized at this point. This is a partial revert, but with the doorbell assignment fixed so the proper doorbell index is set before it's used. Fixes: e3163bc8ffdfdb ("drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega") Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: skhan@linuxfoundation.org Cc: stable@vger.kernel.org
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#
59c43748 |
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09-Sep-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega This mirrors what we do for other asics and this way we are sure the sdma doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. However, the statement says that it applies to multimedia as well, but the VCN code currently initializes doorbells after GFX and there are no known issues there. In my testing at least I don't see any problems on SDMA. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
db101097 |
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09-Sep-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega This mirrors what we do for other asics and this way we are sure the ih doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. In this case IH is initialized before GFX, so there should be no issue. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e3163bc8 |
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09-Sep-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega This mirrors what we do for other asics and this way we are sure the sdma doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. However, the statement says that it applies to multimedia as well, but the VCN code currently initializes doorbells after GFX and there are no known issues there. In my testing at least I don't see any problems on SDMA. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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dc1d85cb |
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09-Sep-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move nbio ih_doorbell_range() into ih code for vega This mirrors what we do for other asics and this way we are sure the ih doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. In this case IH is initialized before GFX, so there should be no issue. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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e24d0e91 |
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29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c This data has no dependencies, so encapsulate it all within amdgpu_discovery.c. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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25faeddc |
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25-Mar-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expand cg_flags from u32 to u64 With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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72a98763 |
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10-Mar-2022 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amd: fix gfx hang on renoir in IGT reload test [why] CP hangs in igt reloading test on renoir, more precisely, hangs on the second time insmod. [how] mode2 reset can make it recover, and mode2 reset only effects gfx core, dcn and the screen will not be impacted. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1f211a82 |
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14-Feb-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: centrally calls the .ras_fini function of all ras blocks centrally calls the .ras_fini function of all ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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667c7091 |
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16-Feb-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Optimize xxx_ras_fini function of each ras block 1. Move the variables of ras block instance members from specific xxx_ras_fini to general ras_fini call. 2. Function calls inside the modules only use parameters passed from xxx_ras_fini instead of ras block instance members. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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01d468d9 |
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16-Feb-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Modify .ras_fini function pointer parameter Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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89bfcd82 |
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17-Feb-2022 |
Chen Gong <curry.gong@amd.com> |
drm/amdgpu: do not enable asic reset for raven2 The GPU reset function of raven2 is not maintained or tested, so it should be very unstable. Now the amdgpu_asic_reset function is added to amdgpu_pmops_suspend, which causes the S3 test of raven2 to fail, so the asic_reset of raven2 is ignored here. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by: Chen Gong <curry.gong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0ab5d711 |
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16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Refactor `amdgpu_aspm` to be evaluated per device Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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867e24ca |
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13-Feb-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: define amdgpu_ras_late_init to call all ras blocks' .ras_late_init Define amdgpu_ras_late_init to call all ras blocks' .ras_late_init. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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caae42f0 |
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13-Feb-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Optimize xxx_ras_late_init function of each ras block 1. Move calling ras block instance members from module internal function to the top calling xxx_ras_late_init. 2. Module internal function calls can only use parameter variables of xxx_ras_late_init instead of ras block instance members. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e506db59 |
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20-Jan-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: disable MMHUB PG for Picasso MMHUB PG needs to be disabled for Picasso for stability reasons. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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04022982 |
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10-Jan-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common helper to read bios from rom create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2e54fe5d |
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04-Jan-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Modify nbio block to fit for the unified ras block data and ops 1.Modify nbio block to fit for the unified ras block data and ops. 2.Change amdgpu_nbio_ras_funcs to amdgpu_nbio_ras, and the corresponding variable name remove _funcs suffix. 3.Remove the const flag of mmhub ras variable so that nbio ras block can be able to be inserted into amdgpu device ras block link list. 4.Invoke amdgpu_ras_register_ras_block function to register nbio ras block into amdgpu device ras block link list. 5.Remove the redundant code about nbio in amdgpu_ras.c after using the unified ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1e2be869 |
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17-Feb-2022 |
Chen Gong <curry.gong@amd.com> |
drm/amdgpu: do not enable asic reset for raven2 The GPU reset function of raven2 is not maintained or tested, so it should be very unstable. Now the amdgpu_asic_reset function is added to amdgpu_pmops_suspend, which causes the S3 test of raven2 to fail, so the asic_reset of raven2 is ignored here. Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Signed-off-by: Chen Gong <curry.gong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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f626dd0f |
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20-Jan-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: disable MMHUB PG for Picasso MMHUB PG needs to be disabled for Picasso for stability reasons. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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326db0dc |
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13-Dec-2021 |
Yann Dirson <ydirson@free.fr> |
amdgpu: fix some comment typos Signed-off-by: Yann Dirson <ydirson@free.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cace4bff |
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25-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: check df_funcs and its callback pointers in case they are not avaiable in early phase Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e3993811 |
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04-Nov-2021 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Fix MMIO HDP flush on SRIOV Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d3a21f7e |
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04-Nov-2021 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Fix MMIO HDP flush on SRIOV Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7092432e |
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11-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop soc15_set_ip_blocks() No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1d789535 |
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04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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75a07bcd |
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04-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: convert to IP version checking Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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91e9db33 |
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30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: get rev_id in soc15_common_early_init for consistency with other SoCs. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
994470b2 |
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30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: export common IP functions So they can be driven by IP discovery table. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2485e275 |
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30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: make soc15_common_ip_funcs static It's not used outside of soc15.c Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
192fb630 |
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25-Aug-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: disable GFX CGCG in aldebaran disable GFX CGCG and CGLS to workaround a hardware issue found in aldebaran. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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733ee71a |
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18-Jun-2021 |
Ryan Taylor <Ryan.Taylor@amd.com> |
drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3) Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
222e0a71 |
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21-Jul-2021 |
Candice Li <candice.li@amd.com> |
drm/amd/amdgpu: add consistent PSP FW loading size checking Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9075096b |
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13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6505d6fc |
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13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9f6a7857 |
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22-Jun-2021 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move apu flags initialization to the start of device init In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a9dc23be |
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21-Apr-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
295c4f51 |
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18-May-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add video_codecs query support for aldebaran Add video_codecs query support for aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8ef4f94a |
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14-May-2021 |
Changfeng <Changfeng.Zhu@amd.com> |
drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0064b0ce |
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10-May-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/pm: enable ASPM by default Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8ab0d6f0 |
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04-May-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Rename to ras_*_enabled Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
acdae216 |
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03-May-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Remove redundant ras->supported Remove redundant ras->supported, as this value is also stored in adev->ras_features. Use adev->ras_features, as that supercedes "ras", since the latter is its member. The dependency goes like this: ras <== adev->ras_features <== hw_supported, and is read as "ras depends on ras_features, which depends on hw_supported." The arrows show the flow of information, i.e. the dependency update. "hw_supported" should also live in "adev". Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a8f76887 |
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02-May-2021 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: set vcn mgcg flag for picasso enable vcn mgcg flag for picasso. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
78871b6c |
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28-Apr-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: enable ras error count query and reset for HDP add hdp block ras error query and reset support in amdgpu ras error count query and reset interface Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ab95cb3e |
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18-May-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add video_codecs query support for aldebaran Add video_codecs query support for aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dbd1003d |
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14-May-2021 |
Changfeng <Changfeng.Zhu@amd.com> |
drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
3666f83a |
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02-May-2021 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: set vcn mgcg flag for picasso enable vcn mgcg flag for picasso. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9d015c0d |
|
14-Apr-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: enable ASPM on vega enable ASPM on vega to save the power without the performance hurt. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6e36f231 |
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02-Apr-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: split nbio callbacks into ras and non-ras ones nbio ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split nbio callbacks into ras and non-ras ones so gpu driver only initializes nbio ras callbacks when it manages nbio ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c6ce68e6 |
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19-Mar-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: label these APIs used internally as static Also drop unnecessary header file and declarations. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50ca2522 |
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02-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Enable VCN/JPEG CG on aldebaran Enable clockgating for VCN and JPEG blocks on aldebaran Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
48a6379a |
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05-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add clock gating support for aldebaran Aldebaran clock gating support for GFX,SDMA,IH blocks VCN/JPEG blocks are excluded in this patch, to be enabled later Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd937973 |
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17-Dec-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn dpg mode on aldebaran Enable vcn dpg mode on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fdb1fdef |
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17-Dec-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn and jpeg on aldebaran Enable vcn and jpeg 2.6 on aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd7228ab |
|
22-Dec-2020 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Enable swsmu block on aldebaran Enable smu13 block on aldebaran Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
10c71e6c |
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30-Nov-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to vega20 ih block for aldebaran replace vega10 ih block with vega20 ih block for aldebaran. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c03e584 |
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19-Nov-2020 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:add smu mode1/2 support for aldebaran Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4f668d3d |
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11-Nov-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: initialize external rev_id for aldebaran add exteranal rev_id for aldebaran Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cf7821a8 |
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21-Aug-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: comments out vcn/jpeg ip blocks for aldebaran vcn fw front door loading is not functional. comments out vcn/jpeg ip blocks so people can load amdgpu driver without specify ip_mask module parameter. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f8db121e |
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06-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/jpeg: enable JPEG on aldebaran enable JPEG on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9f386fd3 |
|
06-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: enable VCN on aldebaran Enable VCN on aldebaran Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
31691b8d |
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21-Oct-2020 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: define address map for host xgmi link (v3) This applies to AMD Accelerated Processing Platforms that support host gpu interconnect throguh a special link (xgmi). Aldebaran systems will support this special feature for utilizing the benefits of host-gpu cache coherence. This change outlines the basic framework for mapping the GPU VRAM (HBM) to system address space making it accesible to the host but managed by the amdgpu driver since this region is marked as reserved memory in host address space by the underlying system firmware. v2: switch to smuio callback function to check the type of host-gpu interface (Hawking) v3: use hub callbacks rather than direct function calls (Alex) Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
efce1000 |
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05-Apr-2020 |
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> |
drm/amdgpu: enable xgmi support for Aldebaran Like its predecessors Aldebran also supports advanced high bandwidth GPU-GPU communication interface known as xgmi. This enables the basic xgmi support while refactoring the code slightly. Detection of xgmi link between host cpu and gpu will be introduced in a different patch. Reviewed-by: Oak Zeng <oak.zeng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7914a0cd |
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16-Oct-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: initialize smuio callbacks for aldebaran initialize smuio v13_0 callbacks for aldebaran Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9fbd96a1 |
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26-Apr-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: enable psp v13 ip block for aldebaran Add psp v13 ip block to soc ip init list for aldebaran Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7906af5e |
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11-Nov-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add soc15 common ip block support for aldebaran Initialize aldebaran common ip block Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
42b72608 |
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05-Sep-2020 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add register base init for aldebaran (v2) v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6f786950 |
|
02-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/codec: drop the internal codec index And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b246e8b |
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07-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3) For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6e80fb8a |
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16-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Set reference clock to 100Mhz on Renoir (v2) Fixes the rlc reference clock used for GPU timestamps. Value is 100Mhz. Confirmed with hardware team. v2: reword commit message. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1480 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
1176a1e0 |
|
04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: add PCI reset support Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
278cdb68 |
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11-Aug-2020 |
mengwang <mengbing.wang@amd.com> |
drm/amdgpu: add new device id for Renior add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by: mengwang <mengbing.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.10.x
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#
455d40c9 |
|
28-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: switch hdp callback functions for hdp v4 Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. V2: clean up hdp reset ras error count function. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
320a2e0c |
|
30-Nov-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to vega20 ih block for vega20/arcturus replace navi10 ih block with vega20 ih block for vega20 and arcturus Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53f1e7f6 |
|
11-Aug-2020 |
mengwang <mengbing.wang@amd.com> |
drm/amdgpu: add new device id for Renior add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by: mengwang <mengbing.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.10.x
|
#
8473c138 |
|
23-Oct-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: disable rom clock gating support for APUs ROM clock gating enable/disable is not supported on APU platform. (i.e. CGTT_ROM_CLK_CTRL0 register is not availabe on APU). SMUIO callbacks will check APU flag before enable/disable rom clock gating, and skip the programming. Accordingly, query clock gating status through CGTT_ROM_CLK_CTRL0 also doesn't support on APU platform. The change applies to RAVEN/RAVEN2/PICASSO/RENOIR. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0e961589 |
|
20-Oct-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to use smuio callbacks for AI family Switch to smuio callbacks: use smuio v9_0 callbacks for Vega10/12, smuio v11_0 callbacks for Vega20/Arcturus. APUs don't support enable/disable rom clock gating and also don't support read bios from rom. So APU flag check is needed in clock gating callbacks and asic funciton for read bios from rom to prevent access unknown offset on APU. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aee68369 |
|
05-Nov-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: add soc15 common ip block support for green_sardine (v3) This patch adds common ip support for green_sardine. v2: use apu flags, squash in CG/PG enablement v3: rebase Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6d2b0fb |
|
29-Oct-2020 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amd/amdgpu: Disable VCN DPG mode for Picasso Concurrent operation of VCN and JPEG decoder in DPG mode is causing ring timeout due to power state. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
94ba290d |
|
02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu: improve code indentation and alignment General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch covers various .c files for this driver. Issue reported by checkpatch script. Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1059360 |
|
26-Mar-2020 |
Alex Sierra <alex.sierra@amd.com> |
drm/amdgpu: replace ih ip block for vega20 and arcturus [Why] Vega20 and Arcturus asics use oss 5.0 version. [How] Replace ih ip block by navi10 for vega20 and arcturus. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a10aad13 |
|
29-Oct-2020 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amd/amdgpu: Disable VCN DPG mode for Picasso Concurrent operation of VCN and JPEG decoder in DPG mode is causing ring timeout due to power state. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
33eade2c |
|
01-Oct-2020 |
Dirk Gouders <dirk@gouders.net> |
drm/amdgpu: fix NULL pointer dereference for Renoir Commit c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") introduced a NULL pointer dereference when booting with amdgpu.discovery=0, because it removed the call of vega10_reg_base_init() for that case. Fix this by calling that funcion if amdgpu_discovery == 0 in addition to the case that amdgpu_discovery_reg_base_init() failed. Fixes: c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") Signed-off-by: Dirk Gouders <dirk@gouders.net> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5baf4150 |
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05-Nov-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: add soc15 common ip block support for green_sardine (v3) This patch adds common ip support for green_sardine. v2: use apu flags, squash in CG/PG enablement v3: rebase Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ae78708 |
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01-Oct-2020 |
Dirk Gouders <dirk@gouders.net> |
drm/amdgpu: fix NULL pointer dereference for Renoir Commit c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") introduced a NULL pointer dereference when booting with amdgpu.discovery=0, because it removed the call of vega10_reg_base_init() for that case. Fix this by calling that funcion if amdgpu_discovery == 0 in addition to the case that amdgpu_discovery_reg_base_init() failed. Fixes: c1cf79ca5ced46 ("drm/amdgpu: use IP discovery table for renoir") Signed-off-by: Dirk Gouders <dirk@gouders.net> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
705a2b5b |
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15-Sep-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to indirect reg access helper Switch WREG32/RREG32_PCIE to use indirect reg access helper for soc15 and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1dd4aa6 |
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23-Aug-2020 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix consecutive DPC recovery failures. Cache the PCI state on boot and before each case where we might loose it. v2: Add pci_restore_state while caching the PCI state to avoid breaking PCI core logic for stuff like suspend/resume. v3: Extract pci_restore_state from amdgpu_device_cache_pci_state to avoid superflous restores during GPU resets and suspend/resumes. v4: Style fixes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b0a2db9b |
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19-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add pre_asic_init callback for SOC15 We need to restore some registers prior to running asic init to work around a firmware bug. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50166d1c |
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01-Jun-2020 |
Prike.Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable HDP clock gatting Enabe HDP SD/DS clock gatting in Renoir series. Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11043b7a |
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10-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: note what type of reset we are using When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
273da6ff |
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14-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: add module parameter choose reset mode Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d95f09ac |
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22-Jun-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: move reg base init forward for soc15 Init soc15 reg base early enough so we can touch mailbox related registers in request full access for sriov before set_ip_blocks, vi&nv arch doesn't use reg base in virt ops. v2: fix reg_base_init missed in bare metal case. Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1299461 |
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22-Jun-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: request init data in virt detection Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks. Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
207f0f13 |
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08-Jun-2020 |
Prike.Liang <Prike.Liang@amd.com> |
drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base accessing The failed case is no SDMA1 IP for Renoir discovery table while in accessing SDMA1 reg base, thus need have nullptr test for soc15_read_register invoked in MMR addres space inquire opt. Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1cf79ca |
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28-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use IP discovery table for renoir Rather than relying on gpu info firmware. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
54f78a76 |
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15-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add apu flags (v2) Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
028cfb24 |
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10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dadce777 |
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10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e520859c |
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10-Feb-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable VCN2.5 DPG mode for Arcturus Enable VCN2.5 DPG mode for arcturus after below items are applied. ASD: 0x21000023 SOS: 0x17003B VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 VBIOS: 23 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3aa0115d |
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03-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1c2cd3f |
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04-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20 The ROMC_INDEX/DATA offset was changed to e4/e5 since from smuio_v11 (vega20/arcturus). Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-by: Candice Li <Candice.Li@amd.com> Reviewed-by: Candice Li <Candice.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a0dd3d9 |
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04-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20 The ROMC_INDEX/DATA offset was changed to e4/e5 since from smuio_v11 (vega20/arcturus). Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-by: Candice Li <Candice.Li@amd.com> Reviewed-by: Candice Li <Candice.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a89ad9b |
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02-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add reset_ras_error_count function for HDP HDP ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c657b936 |
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11-Feb-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: fix xclk for raven It's 25 Mhz (refclk / 4). This fixes the interpretation of the rlc clock counter. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
b90c4d66 |
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11-Feb-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: fix xclk for raven It's 25 Mhz (refclk / 4). This fixes the interpretation of the rlc clock counter. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
276cc929 |
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14-Jan-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: original raven doesn't support full asic reset So don't use it. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a9d4fe2f |
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20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bdf84a80 |
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14-Jan-2020 |
Joseph Greathouse <Joseph.Greathouse@amd.com> |
drm/amdgpu: Create generic DF struct in adev The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e7ddb878 |
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07-Jan-2020 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable VCN2.5 IP block for Arcturus With default PSP FW loading Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9530273e |
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07-Jan-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: cover the powerplay implementation details V3 This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c2a801af |
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09-Dec-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
amd/amdgpu/sriov enable onevf mode for ARCTURUS VF Before, initialization of smu ip block would be skipped for sriov ASICs. But if there's only one VF being used, guest driver should be able to dump some HW info such as clks, temperature,etc. To solve this, now after onevf mode is enabled, host driver will notify guest. If it's onevf mode, guest will do smu hw_init and skip some steps in normal smu hw_init flow because host driver has already done it for smu. With this fix, guest app can talk with smu and dump hw information from smu. v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled. v3: refine is_support_sw_smu and fix some indentation issue. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b8ab58f3 |
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24-Dec-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: add check for baco support on Arcturus This is used to determine whether runtime pm can be supported or not. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ab5999de |
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16-Dec-2019 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu: enable VCN0 and VCN1 sriov instances support for Arcturus v1: compared to bare-metal: sriov support psp loading VCN firmware; only one encoding ring would be used in each instance. v2: keep unchange for bare-metal VCN2.5 hw_init, just add a flag with sriov and also remove multiple lines. v3: squash in warning fix Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c9ffa427 |
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30-Oct-2019 |
Yintian Tao <yttao@amd.com> |
drm/amd/powerplay: enable pp one vf mode for vega10 Originally, due to the restriction from PSP and SMU, VF has to send message to hypervisor driver to handle powerplay change which is complicated and redundant. Currently, SMU and PSP can support VF to directly handle powerplay change by itself. Therefore, the old code about the handshake between VF and PF to handle powerplay will be removed and VF will use new the registers below to handshake with SMU. mmMP1_SMN_C2PMSG_101: register to handle SMU message mmMP1_SMN_C2PMSG_102: register to handle SMU parameter mmMP1_SMN_C2PMSG_103: register to handle SMU response v2: remove module parameter pp_one_vf v3: fix the parens v4: forbid vf to change smu feature v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute v6: change skip condition at vega10_copy_table_to_smc Signed-off-by: Yintian Tao <yttao@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
feffbaac |
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26-Nov-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add condition to enable baco for ras recovery Switch to baco reset method for ras recovery if the PMFW supported. If not, keep the original reset method. v2: revise the condition Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d5159591 |
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06-Dec-2019 |
Thong Thai <thong.thai@amd.com> |
Revert "drm/amdgpu: enable VCN DPG on Raven and Raven2" This reverts commit a4840d91c984f93b2acdcd44441d624bbc1af0d2. Reverting due to power efficiency issues seen on Raven 1 and 2 when DPG mode is enabled. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e416fdb6 |
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25-Nov-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/amdgpu/sriov skip jpeg ip block for ARCTURUS VF Currently ARCTURUS VF doesn't support jpeg ip block. Skip jpeg ip block in case guest driver load fail. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Zhexi Zhang <zhexi.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11520f27 |
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28-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: split swSMU baco_reset into enter and exit BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
988eb9ff |
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15-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add supports_baco callback for soc15 asics. (v2) BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. v2: drop unrelated struct cleanup Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0a650c1d |
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04-Nov-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: add Arcturus baco reset support Enable baco reset support on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
761e0923 |
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15-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: move struct definition around to align with other soc15 asics Move reset_method next to reset callback to match the struct layout and the other definition in this file. Reviewed-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c74e590 |
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11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable Arcturus JPEG2.5 block It also doen't care about FW loading type, so enabling it directly. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e89e2237 |
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11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks Arcturus VCN and JPEG only got CG support, and no PG support Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5be45a26 |
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08-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir By adding JPEG IP block to the family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
099d66e4 |
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11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add PG and CG for JPEG2.0 And enable them for Navi1x and Renoir Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
77a31602 |
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29-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/renoir: move gfxoff handling into gfx9 module To properly handle the option parsing ordering. Reviewed-by: Yong Zhao <yong.zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ad4d81dc |
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29-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/renoir: move gfxoff handling into gfx9 module To properly handle the option parsing ordering. Reviewed-by: Yong Zhao <yong.zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a4840d91 |
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31-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: enable VCN DPG on Raven and Raven2 It's safe to enable dynamic VCN powergating on raven and raven2 for increased power savings. Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
664fe85a |
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22-Oct-2019 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: Allow reading more status registers on si/cik Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5337aae9 |
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15-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: add support for baco reset with swSMU Add support for vega20 when the swSMU path is used. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
31fa2991 |
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04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove in_baco_reset hack It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
956f6705 |
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11-Oct-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence Workaround to make RAS recovery work in BACO reset. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
324fb7ad |
|
02-Oct-2019 |
Arnd Bergmann <arnd@arndb.de> |
drm/amdgpu: hide another #warning An earlier patch of mine disabled some #warning statements that get in the way of build testing, but then another instance was added around the same time. Remove that as well. Fixes: b5203d16aef4 ("drm/amd/amdgpu: hide #warning for missing DC config") Fixes: e1c14c43395c ("drm/amdgpu: Enable DC on Renoir") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c9a0c66 |
|
01-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't increment vram lost if we are in hibernation We reset the GPU as part of our hibernation sequence so we need to make sure we don't mark vram as lost in that case. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
21889cec |
|
26-Sep-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/amdgpu/sriov ip block setting of Arcturus Add ip block setting for Arcturus SRIOV 1.PSP need to be initialized before IH. 2.SMU doesn't need to be initialized at kmd driver. 3.Arcturus doesn't support DCE hardware,it needs to skip register access to DCE. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
227f7d58 |
|
24-Sep-2019 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: add IH cg support on soc15 project enable/disable IH clock gating on soc15 projects. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de9bbd52 |
|
18-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add ras fini for nbio add a common nbio ras fini implementation to cleanup nbio ras framework Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
90a08351 |
|
19-Sep-2019 |
chen gong <curry.gong@amd.com> |
drm/amdgpu: Use mode2 mode to perform GPU RESET for Renoir Renoir need to use mode2 mode to implement GPU RESET Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a018e5a8 |
|
22-Sep-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: disable vcn ip block for front door loading on Arcturus Needs more work to enable via front door loading. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2011eaea |
|
17-Sep-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add psp ip block for arct enable psp block for firmware loading and other security feature setup. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
29174a43 |
|
02-Oct-2019 |
Arnd Bergmann <arnd@arndb.de> |
drm/amdgpu: hide another #warning An earlier patch of mine disabled some #warning statements that get in the way of build testing, but then another instance was added around the same time. Remove that as well. Fixes: b5203d16aef4 ("drm/amd/amdgpu: hide #warning for missing DC config") Fixes: e1c14c43395c ("drm/amdgpu: Enable DC on Renoir") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
49379032 |
|
01-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't increment vram lost if we are in hibernation We reset the GPU as part of our hibernation sequence so we need to make sure we don't mark vram as lost in that case. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cde85ac2 |
|
06-Sep-2019 |
Philip Yang <Philip.Yang@amd.com> |
drm/amdgpu: check if nbio->ras_if exist To avoid NULL function pointer access. This happens on VG10, reboot command hangs and have to power off/on to reboot the machine. This is serial console log: [ OK ] Reached target Unmount All Filesystems. [ OK ] Reached target Final Step. Starting Reboot... [ 305.696271] systemd-shutdown[1]: Syncing filesystems and block devices. [ 306.947328] systemd-shutdown[1]: Sending SIGTERM to remaining processes... [ 306.963920] systemd-journald[1722]: Received SIGTERM from PID 1 (systemd-shutdow). [ 307.322717] systemd-shutdown[1]: Sending SIGKILL to remaining processes... [ 307.336472] systemd-shutdown[1]: Unmounting file systems. [ 307.454202] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro [ 307.480523] systemd-shutdown[1]: All filesystems unmounted. [ 307.486537] systemd-shutdown[1]: Deactivating swaps. [ 307.491962] systemd-shutdown[1]: All swaps deactivated. [ 307.497624] systemd-shutdown[1]: Detaching loop devices. [ 307.504418] systemd-shutdown[1]: All loop devices detached. [ 307.510418] systemd-shutdown[1]: Detaching DM devices. [ 307.565907] sd 2:0:0:0: [sda] Synchronizing SCSI cache [ 307.731313] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 307.738802] #PF: supervisor read access in kernel mode [ 307.744326] #PF: error_code(0x0000) - not-present page [ 307.749850] PGD 0 P4D 0 [ 307.752568] Oops: 0000 [#1] SMP PTI [ 307.756314] CPU: 3 PID: 1 Comm: systemd-shutdow Not tainted 5.2.0-rc1-kfd-yangp #453 [ 307.764644] Hardware name: ASUS All Series/Z97-PRO(Wi-Fi ac)/USB 3.1, BIOS 9001 03/07/2016 [ 307.773580] RIP: 0010:soc15_common_hw_fini+0x33/0xc0 [amdgpu] [ 307.779760] Code: 89 fb e8 60 f5 ff ff f6 83 50 df 01 00 04 75 3d 48 8b b3 90 7d 00 00 48 c7 c7 17 b8 530 [ 307.799967] RSP: 0018:ffffac9483153d40 EFLAGS: 00010286 [ 307.805585] RAX: 0000000000000000 RBX: ffff9eb299da0000 RCX: 0000000000000006 [ 307.813261] RDX: 0000000000000000 RSI: ffff9eb29e3508a0 RDI: ffff9eb29e350000 [ 307.820935] RBP: ffff9eb299da0000 R08: 0000000000000000 R09: 0000000000000000 [ 307.828609] R10: 0000000000000000 R11: 0000000000000000 R12: ffff9eb299dbd1f8 [ 307.836284] R13: ffffffffc04f8368 R14: ffff9eb29cebd130 R15: 0000000000000000 [ 307.843959] FS: 00007f06721c9940(0000) GS:ffff9eb2a18c0000(0000) knlGS:0000000000000000 [ 307.852663] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 307.858842] CR2: 0000000000000000 CR3: 000000081d798005 CR4: 00000000001606e0 [ 307.866516] Call Trace: [ 307.869169] amdgpu_device_ip_suspend_phase2+0x80/0x110 [amdgpu] [ 307.875654] ? amdgpu_device_ip_suspend_phase1+0x4d/0xd0 [amdgpu] [ 307.882230] amdgpu_device_ip_suspend+0x2e/0x60 [amdgpu] [ 307.887966] amdgpu_pci_shutdown+0x2f/0x40 [amdgpu] [ 307.893211] pci_device_shutdown+0x31/0x60 [ 307.897613] device_shutdown+0x14c/0x1f0 [ 307.901829] kernel_restart+0xe/0x50 [ 307.905669] __do_sys_reboot+0x1df/0x210 [ 307.909884] ? task_work_run+0x73/0xb0 [ 307.913914] ? trace_hardirqs_off_thunk+0x1a/0x1c [ 307.918970] do_syscall_64+0x4a/0x1c0 [ 307.922904] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 307.928336] RIP: 0033:0x7f0671cf8373 [ 307.932176] Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 89 fa be 69 19 128 [ 307.952384] RSP: 002b:00007ffdd1723d68 EFLAGS: 00000202 ORIG_RAX: 00000000000000a9 [ 307.960527] RAX: ffffffffffffffda RBX: 0000000001234567 RCX: 00007f0671cf8373 [ 307.968201] RDX: 0000000001234567 RSI: 0000000028121969 RDI: 00000000fee1dead [ 307.975875] RBP: 00007ffdd1723dd0 R08: 0000000000000000 R09: 0000000000000000 [ 307.983550] R10: 0000000000000002 R11: 0000000000000202 R12: 00007ffdd1723dd8 [ 307.991224] R13: 0000000000000000 R14: 0000001b00000004 R15: 00007ffdd17240c8 [ 307.998901] Modules linked in: xt_MASQUERADE nfnetlink iptable_nat xt_addrtype xt_conntrack nf_nat nf_cos [ 308.026505] CR2: 0000000000000000 [ 308.039998] RIP: 0010:soc15_common_hw_fini+0x33/0xc0 [amdgpu] [ 308.046180] Code: 89 fb e8 60 f5 ff ff f6 83 50 df 01 00 04 75 3d 48 8b b3 90 7d 00 00 48 c7 c7 17 b8 530 [ 308.066392] RSP: 0018:ffffac9483153d40 EFLAGS: 00010286 [ 308.072013] RAX: 0000000000000000 RBX: ffff9eb299da0000 RCX: 0000000000000006 [ 308.079689] RDX: 0000000000000000 RSI: ffff9eb29e3508a0 RDI: ffff9eb29e350000 [ 308.087366] RBP: ffff9eb299da0000 R08: 0000000000000000 R09: 0000000000000000 [ 308.095042] R10: 0000000000000000 R11: 0000000000000000 R12: ffff9eb299dbd1f8 [ 308.102717] R13: ffffffffc04f8368 R14: ffff9eb29cebd130 R15: 0000000000000000 [ 308.110394] FS: 00007f06721c9940(0000) GS:ffff9eb2a18c0000(0000) knlGS:0000000000000000 [ 308.119099] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 308.125280] CR2: 0000000000000000 CR3: 000000081d798005 CR4: 00000000001606e0 [ 308.135304] printk: systemd-shutdow: 3 output lines suppressed due to ratelimiting [ 308.143518] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 [ 308.151798] Kernel Offset: 0x15000000 from 0xffffffff81000000 (relocation range: 0xffffffff80000000-0xff) [ 308.171775] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1d59e00 |
|
02-Sep-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/amdgpu: add sw_fini interface for df_funcs add sw_fini interface of df_funcs. This interface will remove sysfs file of df_cntr_avail function. The old behavior only create sysfs of df_cntr_avail in sw_init, but never remove it for lack of sw_fini interface. With this,driver will report create sysfs fail when it's loaded for the second time. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Jonathan Kim <Jonathan.Kim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
22e1d14f |
|
29-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to amdgpu_ras_late_init for nbio v7_4 (v2) call helper function in late init phase to handle ras init for nbio ip block v2: init local var r to 0 in case the function return failure on asics that don't have ras_late_init implementation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bebc0762 |
|
23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure no functional change, just switch to new structures Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e1c14c43 |
|
08-Aug-2019 |
Roman Li <Roman.Li@amd.com> |
drm/amdgpu: Enable DC on Renoir Enable DC support for renoir. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3526257 |
|
27-Aug-2019 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: introduce vram lost for reset (v2) for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
85400984 |
|
15-Aug-2019 |
Thong Thai <thong.thai@amd.com> |
drm/amdgpu: enable VCN DPG for Renoir This will enable indirect SRAM loading for VCN DPG mode initialization. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a868d8b |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable SDMA power gating for rn Enable SDMA PG flag during device ip early init. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8db63b7c |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable DF clock gating for rn Enable DF clock gating during DF IP early init. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e2ef3b70 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable athub clock gating for rn Enable athub MG and LS clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
91ec8bbb |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable IH clock gating for rn Enable IH clock gating during IH block initialized. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
753c929c |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable vcn clock gating for rn Enable VCN middle grain clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de273070 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable rom clock gating for rn Enable rom light sleep clock gating. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9deac0a4 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable HDP clock gating for rn Enable HDP light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d98930f5 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable BIF clock gating for rn Enable BIF light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ef0e7d08 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable sdma clock gating for rn Enable sdma middle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a2d15255 |
|
02-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable mmhub clock gating for rn Enable mmhub midle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec3636a5 |
|
01-Aug-2019 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable gfx clock gating for rn Enable gfx cg/mg/cp etc clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9f21e9ee |
|
16-Jul-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add and enable gfxoff feature This patch updates gfxoff feature. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97222cfa |
|
09-Aug-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir 1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5dbbe6a7 |
|
24-Jul-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu/powerplay: add smu ip block for renoir (v2) add swSMU [smu_v12_0] for renoir v2: whitespace fixes (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b05f65d7 |
|
15-Aug-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
|
#
98f58ada |
|
15-Aug-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Cc: stable@vger.kernel.org
|
#
c43b849f |
|
26-Jul-2019 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Use new mode2 reset interface for RV. Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f78e007f |
|
12-Aug-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: enable clock gating for renoir enable gfx&common clock gating for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
279ba48e |
|
15-Jul-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VCN2.0 to Renoir IP blocks Thus enable VCN2.0 for Renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a7a0bdb |
|
09-Aug-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add psp_v12_0 for renoir (v2) 1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e09ce481 |
|
07-Apr-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add asic funcs for renoir add asic funcs for renoir, init soc15_asic_funcs Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b1326bbc |
|
24-Jul-2019 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: enable dce virtual ip module for Renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
05e1f0e0 |
|
24-Jul-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: set ip blocks for renoir Enable ip blocks for renoir. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
080deab6 |
|
24-Jul-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add soc15 common ip block support for renoir This patch adds common ip support for renoir. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a840159c |
|
09-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: enable mmhub clock gating for Arcturus Init MC_MGCG/LS flag. Also apply to athub CG. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f9da7c43 |
|
09-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add GFX_CP_LS flag to Arcturus Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before drm/amdgpu: enable gfx clock gating for Arcturus Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7ee1995 |
|
07-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: enable sdma clock gating for Arcturus Init sdma MGCG/LS flag Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5d111f5b |
|
07-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: enable hdp clock gating for Arcturus Init hdp MGCG/LS flag as Vega20 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6acb87ac |
|
07-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add hdp clock gating for Arcturus Add hdp CGLS for Arcturus in set common clockgating function Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6b76ce62 |
|
07-Aug-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: enable gfx clock gating for Arcturus Init gfx MGCG/LS and CGCG/LS flag. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
612e4ed9 |
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31-Jul-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Fix pcie_bw on Vega20 The registers used for VG20 are different in that certain performance counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add a new vg20_get_pcie_usage to reflect this change. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
19ed70ff |
|
01-Aug-2019 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Add amdgpu_asic_funcs.reset_method for Vega20 Fixes GPU reset crash. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4cd4c5c0 |
|
30-Jul-2019 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup vega10 SRIOV code path we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4fa1c6a6 |
|
24-Jul-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add RREG64/WREG64(_PCIE) operations add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe089e1d |
|
12-Jul-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: enable arcturus powerplay Arcturus powerplay is ready to use. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ee360c0b |
|
23-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add reset_method asic callback for soc15 APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d57c3d56 |
|
27-Jun-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init arct external rev id Properly set the external silicon revision id. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5fb7c665 |
|
20-May-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: correct ip for mmHDP_READ_CACHE_INVALIDATE register access Use the proper IP index for HDP registers. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
08249a3a |
|
16-Apr-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable VCN2.5 on Arcturus VCN is the video decode and encode engine on Arcturus Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eb39aff7 |
|
20-Mar-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Enable xgmi support for Arcturus xgmi is a high performance cross-GPU communication channel. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7f40581c |
|
19-Dec-2018 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Initialize asic functions for Arcturus After cherry-picking doorbell rework changes from drm-next branch, Arcturus asic functions pointer need to be initialized to init doorbell index for Arcturus. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0e54df05 |
|
10-Sep-2018 |
Le Ma <le.ma@amd.com> |
drm/amdgpu/soc15: add Arcturus common ip blocks Add common IP blocks for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e78705ec |
|
09-Jul-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: dynamically initialize IP offset for Arcturus Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b5203d16 |
|
12-Jul-2019 |
Arnd Bergmann <arnd@arndb.de> |
drm/amd/amdgpu: hide #warning for missing DC config It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9417f703 |
|
15-Jul-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Fix Vega20 Perf counter for pcie_bw The perf counter for Vega20 is 108, instead of 104 which it was on all previous GPUs, so add a check to use the appropriate value. Signed-off-by: Kent Russell <kent.russell@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0172591e |
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24-Jun-2019 |
Ernst Sjöstrand <ernstp@gmail.com> |
drm/amd/amdgpu: Indent AMD_IS_APU properly Reported by smatch: drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn: inconsistent indenting And a similar one in si.c. Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e0d07657 |
|
08-Jun-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: update golden setting programming logic Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
44f1bb1f |
|
10-May-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10 Move to the header file. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e4cf4bf5 |
|
19-Jun-2019 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: update df_v3_6 for xgmi perfmons (v2) add pmu attribute groups and structures for perf events. add sysfs to track available df perfmon counters fix overflow handling in perfmon counter reads. v2: squash in fix (Alex) Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47b757fb |
|
09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in remaining files With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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#
394e9a14 |
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27-May-2019 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu: Need to set the baco cap before baco reset For passthrough, after rebooted the VM, driver will do a baco reset before doing other driver initialization during loading driver. For doing the baco reset, it will first check the baco reset capability. So first need to set the cap from the vbios information or baco reset won't be enabled. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d55f33da |
|
17-May-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: skip reset on init Not necessary on soc15 and breaks driver reload on server cards. Acked-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e74609cb |
|
15-May-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vega20: use mode1 reset for RAS and XGMI If RAS or XGMI are enabled, you have to use mode1 reset rather than BACO. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1bff7f6c6 |
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02-May-2019 |
Trigger Huang <Trigger.Huang@amd.com> |
drm/amdgpu: RLC to program regs for Vega10 SR-IOV Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC to program some registers if supported Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
98cad2de |
|
03-Mar-2019 |
Trigger Huang <Trigger.Huang@amd.com> |
drm/amdgpu: Skip setting some regs under Vega10 VF For Vega10 SR-IOV VF, skip setting some regs due to: 1, host will program them 2, avoid VF register programming violations Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d11fd3f |
|
24-Apr-2019 |
Trigger Huang <Trigger.Huang@amd.com> |
drm/amdgpu: initialize PSP before IH under SR-IOV In order to support new PSP feature that PSP may provide interface to program IH CNTL register, initialize PSP before IH under Vega10 SR-IOV VF Signed-off-by: Trigger Huang <Trigger.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dcea6e65 |
|
30-Apr-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add PCIe replay count sysfs file Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88807dc8 |
|
04-Apr-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Remap hdp coherency registers Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL to an empty page in mmio space. We will later map this page to process space so application can flush hdp. This can't be done properly at those registers' original location because it will expose more than desired registers to process space. v2: Use explicit register hole location v3: Moved remapped hdp registers into adev struct v4: Use more generic name for remapped page Expose register offset in kfd_ioctl.h v5: Move hdp register remap function to nbio ip function v6: Fixed operator precedence issue and other bugs Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5887a599 |
|
17-May-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: skip reset on init Not necessary on soc15 and breaks driver reload on server cards. Acked-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
fced5c70 |
|
19-Apr-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: enable MGCG for PCO Enable MGCG for picasso. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
017d75f1 |
|
14-Apr-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable Vega20 BACO reset support PSP SOS firmware needs to be 0x80067 or later. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
39fee32b |
|
14-Mar-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: error out on mode1 reset failure The error return value should be correctly reflected. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c5ccf14 |
|
06-Mar-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: apply Vega20 BACO workaround Applied vdci flush workaround for Vega20 BACO. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3b94fb10 |
|
30-Jan-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amd/powerplay: add limit of pp_feature for smu (v3) Move pp_feature from the struct of amd_powerplay to amdgpu_device. Add pp_feature limit for overdrive interface. v2: put pp_feature into struct amdgpu_pm. v3: merge feature_mask with pp_feature. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dc8e3a0c |
|
09-Jan-2019 |
Kevin Wang <Kevin1.Wang@amd.com> |
drm/amd/powerplay: implement is_support_sw_smu function for new smu add this helper to check new sw-smu support. Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2da5410b |
|
29-Nov-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable new smu ip block for vega20 Switch to new smu ip block since vega20. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f8b18cf4 |
|
10-Feb-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use BACO on vega12 if platform supports it Use BACO for reset of the platform supports it. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7db329e5 |
|
24-Feb-2019 |
Candice Li <candice.li@amd.com> |
Revert "drm/amdgpu: use BACO reset on vega20 if platform support" This reverts commit 2172b89e7c94605380d8c0dedf543c93f0a0b27c. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e4545d3 |
|
30-Jan-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: fix the incorrect external id for raven series This patch fixes the incorrect external id that kernel reports to user mode driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should be 0x21 while rev_id == 1. Reported-by: Crystal Jin <Crystal.Jin@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3680b2a5 |
|
07-Jan-2019 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: check PSP support before adding the ip block So that we do not need to check this in every internal function. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7c94bc82 |
|
14-Jan-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Setting doorbell range registers earlier HW doorbell writing routing policy: writing to doorbell not in SDMA/IH/MM/ACV doorbell range will be routed to CP. So CP doorbell routing depends on doorbell range setting of above blocks. Setting doorbell range of above blocks earlier (soc15_common_hw_init) to make sure CP doorbell writing be routed to CP block. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1f46df61 |
|
14-Jan-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: return proper error codes in baco reset Rather than just -1. Reviewed-by: JimQu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2172b89e |
|
07-Nov-2018 |
Jim Qu <Jim.Qu@amd.com> |
drm/amdgpu: use BACO reset on vega20 if platform support Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e2b6d053 |
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06-Nov-2018 |
Jim Qu <Jim.Qu@amd.com> |
drm/amdgpu: use BACO reset if platform support (v2) It will fall back to use mode1 reset if platform does not support BACO feature. v2: squash in warning fix (Alex) Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9281f12c |
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31-Oct-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: add need_reset_on_init asic callback for SOC15 (v2) SOC15 chips require a reset if the driver was previously loaded because the PSP can only be loaded once between each reset. v2: rebase, handle multiple asic funcs Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b45e18ac |
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03-Jan-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add sysfs file for PCIe usage v5 Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47622ba0 |
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30-Nov-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a xgmi supported flag Use this to track whether an asic supports xgmi rather than checking the asic type everywhere. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c93aa775 |
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19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Doorbell layout for vega20 and future asic This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
062f3807 |
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19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Vega10 doorbell index initialization v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a5d0f456 |
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18-Nov-2018 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amdgpu: Enable HDP memory light sleep Due to the register name and setting change of HDP memory light sleep on Vega20,change accordingly in the driver. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
009d9ed6 |
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30-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Change AI gfx/sdma/smu init sequence initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a3716d3a |
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21-Sep-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu:Enable DPG mode on PCO Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
846311ae |
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26-Apr-2018 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: Exclude MM engines for vega20 virtual device Temporary disable UVD/VCE block if is virtual device Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
741deade |
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13-Sep-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: simplify Raven, Raven2, and Picasso handling Treat them all as Raven rather than adding a new picasso asic type. This simplifies a lot of code and also handles the case of rv2 chips with the 0x15d8 pci id. It also fixes dmcu fw handling for picasso. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
23ecdc61 |
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13-Sep-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: clean up picasso support It's the same as raven so remove the duplicate case. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
520cbe0f |
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19-Jun-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: set CG flags for raven2 (v2) Raven2 does not enable all of the CG flags that raven1 does. v2: rebase (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1879e6a7 |
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15-Jun-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: set external rev id for raven2 It's different from raven1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4cb0becb |
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15-Jun-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move get_rev_id at first before load gpu_info firmware Rev id is used for identifying Raven2 series of chips. So we would better to initialize it at first. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
40c2358b |
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09-Jul-2018 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add ip blocks for picasso (v2) Add PCO IPs. V2: enable VCN as well Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a84d967 |
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24-Aug-2018 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amdgpu: enable vcn powergating for PCO enable vcn pg Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
91468057 |
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20-Aug-2018 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amdgpu: enable mmhub power gating Remove some functions due to the design change. All the mmhub power gating sequence is moved to smu fw.Driver sends the message to enable mmhub powergating.We can also skip the fw version check since the old fw version is in a very early stage and we don't use that fw for release. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a4494fda |
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10-Aug-2018 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amdgpu: Enable SDMA power gating for PCO Enable SDMA power gating Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c7bf583 |
|
07-Aug-2018 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amdgpu: Add pg support for gfxoff for PCO Add pg support for gfxoff. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ad5a67a7 |
|
10-Jul-2018 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add soc15 support for picasso Add the IP blocks, clock and powergating flags, and common clockgating support. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
654f761c |
|
11-May-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add psp 11.0 support for vega20. (v2) Add psp 11.0 code for vega20 and enable it. PSP is the security processor for the GPU. It handles firmware loading and GPU resets among other things. v2: whitespace fix, enable support, adjust reg includes (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6637313 |
|
02-May-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable vega20 powerplay support Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe3c9489 |
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23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add nbio 7.4 support for vega20 (v3) Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25eaa565 |
|
03-Apr-2018 |
Alex Deucher <alexander.deucher@amd.com> |
Revert "drm/amdgpu: Add nbio support for vega20 (v2)" Revert this to add proper nbio 7.4 support. This reverts commit f5b2e1fa321eff20a9418ebd497d8a466f024a85. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
102e4940 |
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27-May-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: typo fix for vega20 cg flags The AMD_CG_SUPPORT_HDP_LS was wrongly written as AMD_CG_SUPPORT_BIF_LS. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
61c8e90d |
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17-May-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Enable VCN static PG by default on RV Enable static VCN powergating by default on Raven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79953a60 |
|
16-May-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Enable VCN CG by default on RV Enable VCN clockgating by default on Raven. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
698758bb |
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04-Apr-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Switch to use df_v3_6_funcs for vega20 (v2) v2: fix whitespace (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
705e98d7 |
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30-Apr-2018 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vg20:Enable UVD/VCE for Vega20 Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
602ed6c6 |
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23-Apr-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Disable ip modules that are not ready yet Please enable above ips on soc15.c when they're available. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3fdbab5f |
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25-Mar-2018 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: update vega20 cg flags (v2) v2: remove duplicate flag. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a95d89e2 |
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23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add nbio support for vega20 (v2) Some register offset in nbio v7.4 are different with v7.0. v2: Use nbio7.0 for now. TODO: add a new nbio 7.4 module (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7c7af6c1 |
|
20-Apr-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu/soc15: Add ip blocks for vega20 (v2) Same as vega10 now. v2: squash in typo fix Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8ee273e5 |
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23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu/soc15: dynamic initialize ip offset for vega20 Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f980d127 |
|
26-Jan-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu/soc15: Set common clockgating for vega20. Same as vega10 for now. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
935be7a0 |
|
26-Jan-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu/soc15:Add vega20 soc15_common_early_init support Set external_rev_id and disable cg,pg for now. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cc3a98cc |
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11-May-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Drop the unused header files in soc15.c. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9ac4b0d9 |
|
14-Dec-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: set CGPG if gfxoff is enabled for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5eeae247 |
|
10-Apr-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gfx9: cache DB_DEBUG2 and make it available to userspace Userspace needs to query this value to work around a hw bug in certain cases. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
adbd4f89 |
|
29-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: implement asic need_full_reset callback Used to check on a per SoC basis whether the SoC needs a full reset of a per IP soft reset. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
070706c0 |
|
28-Mar-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to use df callback functions Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3084eb00 |
|
12-Mar-2018 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/soc15: initialize reg base for vega12 Initialize the IP offsets for vega12. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f559fe2b |
|
14-Dec-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/soc15: Add external_rev_id for vega12. Add external_rev_id for vega12. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e4a38755 |
|
24-Dec-2017 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu/soc15: update vega12 cg_flags Add the appropriate clockgating flags for vega12 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
692069a1 |
|
06-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: add support for vega12 Add the IP blocks, clock and powergating flags, and common clockgating support. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
|
#
699f4795 |
|
15-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Delete dead code when early init Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b905090d |
|
12-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Remove wrapper layer of smu ip functions 1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5494d864 |
|
09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move getting pcie info to common code No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3cdfe700 |
|
09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: always load the psp module Regardless of whether the user has selected psp fw loading or not. It's still needed for GPU reset among other things. There are already guards in place to avoid setting up the full psp if PSP fw loading is not enabled. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
454bbbf9 |
|
09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use adev->firmware to determine whether to load the PSP module The per device firmware load method is limited to what makes sense for that asic rather than whatever arbitrary value may have been set by the user. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19aede77 |
|
09-Mar-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move firmware loading type setup to common code No need to replicate it in several places. Reviewed-by: Rex Zhu <rezhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f75a9a5d |
|
23-Jan-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: don't abuse IP soft reset for adapter reset The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
69882565 |
|
19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add optional ring to *_hdp callbacks This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73c73240 |
|
06-Sep-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add HDP asic callbacks for SOC15 (v2) Needed to flush and invalidate the HDP block using the CPU. v2: use preferred register on soc15. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> (v1)
|
#
400b6afb |
|
13-Dec-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: disable MMHUB power gating on raven MMHUB power gating still has issue, and doesn't work on raven at current. So disable it for the moment. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
041d9d93 |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_get_pcie_info add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2990a1fc |
|
15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename ip block helper functions add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2dd744e0 |
|
08-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop soc15_init_golden_registers The golden register arrays were empty so the function was effectively useless. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bf383fb6 |
|
08-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert nbio to use callbacks (v2) Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4fd09a19 |
|
29-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/admgpu: Reduce the usage of soc15ip.h Remove the header where it's not used. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cd29253f |
|
29-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
946a4d5b |
|
28-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4522824c |
|
27-Nov-2017 |
Shaoyun Liu <Shaoyun.Liu@amd.com> |
drm/amdgpu: Dynamic initialize IP base offset The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fb960bd2 |
|
23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 header files. Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
424d9bb4 |
|
23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 smuio header files. Cleanup asic_reg/vega10/SMUIO folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cde5c34f |
|
23-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 gc header files. Cleanup asic_reg/vega10/GC folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d735f83 |
|
22-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 uvd header files. Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6651c98 |
|
15-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 mp header files. Cleanup asic_reg/vega10/MP folder, remove mp_9_0_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75199b8c |
|
15-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 hdp header files. Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
812f77b7 |
|
15-Nov-2017 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/include:cleanup vega10 sdma0/1 header files. To remove include/asic_reg/vega10 folder,create IP folders sdma0/1. This patch cleanup asic_reg/vega10/SDMA folders. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c47b41a7 |
|
03-Nov-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
76d6172b |
|
29-Sep-2017 |
Ken Wang <Ken.Wang@amd.com> |
drm/amdgpu: correct reference clock value on vega10 Old value from bringup was wrong. Cc: stable@vger.kernel.org Signed-off-by: Ken Wang <Ken.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6622f3a |
|
28-Sep-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu/nbio: use constant nbio_hdp_flush_reg structs. This removes the init path as well, since the init path just did some constant init of some structs. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
35b31f7c |
|
28-Sep-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu/soc15: make the pcie index/data registers constant. These don't seem to change at runtime, and the initialisers are constant data. This could be improved by not selecting the apu/non-apu path on each pcie read/write access. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0bf954c1 |
|
02-Jun-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: enable DC ip module for Raven Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ab587d4a |
|
19-Apr-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: enable dc on vega10 Add the DC display module to drive the DCE12 IP on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
98512bb8 |
|
14-Sep-2017 |
Ken Wang <Ken.Wang@amd.com> |
drm/amdgpu: Add GPU reset functionality for Vega10 V2 Signed-off-by: Ken Wang <Ken.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1a6ec7ed |
|
11-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: drop dead function Maybe a leftover from bringup? Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
833fa075 |
|
06-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: init nbio registers for vega10 Call nbio init registers on hw_init to set up any nbio registers that need initialization at hw init time. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f11fb02 |
|
03-Jul-2017 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: added soc15 support for new se_cac_idx APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
560460f2 |
|
03-Jul-2017 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: added index gc cac read/write apis for vega10 Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
747f6c92 |
|
23-Jun-2017 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add ACG SMU firmware for other vega10 variants Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d05da0e2 |
|
30-Jun-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: unify some atombios/atomfirmware scratch reg functions Now that we use a pointer to the scratch reg start offset, most of the functions were duplicated. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
32622ad8 |
|
19-Jun-2017 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: enable mmhub pg on raven Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d67fed16 |
|
02-Jun-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add virtual display support for raven Same as other asics. If enabled, exposes a user selectable number of virtual displays. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1191d110 |
|
31-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: remove mmhub ip Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
373f5923 |
|
31-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: remove gfxhub ip Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
30db095f |
|
11-May-2017 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu/powerplay/raven: add smu block and enable powerplay Add the ip block and enable powerplay on raven. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f2d7e707 |
|
28-Dec-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add vcn ip block to soc15 Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e2837f6 |
|
11-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/soc15: add psp ip block Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7fda6eca |
|
26-Feb-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add nbio MGCG for raven Add medium grained nbio clockgating implementation. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aecbe64f |
|
04-May-2017 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: apply nbio7 for Raven (v3) nbio handles misc bus io operations. Handle differences between different nbio bus versions. v2: switch checks from RAVEN to APU (Alex) squash in raven rev id fetch squash in fix uninitalized hdp flush reg index for raven v3: add some missed RAVEN to APU checks (Alex) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16f7bf09 |
|
05-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable sdma power gating for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe1a3b2e |
|
05-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable sdma v4 MGCG and LS for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c2cdb0ec |
|
05-May-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable MC MGCG and LS for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c5928a2 |
|
18-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable soc15 clock gating flags for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e5a9eb4 |
|
18-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/soc15: add clock gating functions for raven Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
957c6fe1 |
|
27-Dec-2016 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amd/amdgpu: fill in raven case in soc15 early init Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e0ab9578 |
|
07-Dec-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu/soc15: add Raven golden setting Add the common golden settings for Raven. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1023b797 |
|
07-Dec-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: add Raven ip blocks (v2) Add the IP blocks for RAVEN. v2: drop DC for upstream (Alex) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ab276632 |
|
21-Apr-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/virt: change the place of virt_init_setting Change place of virt_init_setting function so that can cover the cg and pg flags configuration. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3032f350 |
|
11-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop support for per ASIC read registers Only per family registers are still used. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97fcc76b |
|
11-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop support for untouched registers I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
248a1d6f |
|
23-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
drm/amd: fix include notation and remove -Iinclude/drm flag Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
|
#
bfc181af |
|
05-May-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset Need to use the atomfirmware interface rather than atombios since soc15 is atomfirmware based. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
91faed9e |
|
16-Apr-2017 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu/soc15: enable UVD code path for sriov Enable UVD block for SRIOV. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81758c55 |
|
04-Apr-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:invoke new implemented AI MB func Implement the sr-iov mailbox for soc15 asics. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bb5c9ca5 |
|
30-Mar-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:add PSP block only load_type=PSP (v2) SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1fdc639b |
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03-Apr-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: Fix static checker warnings vega10 is the only soc15 asic at the moment so these warnings are invalid, but add a default case to silence the warnings. Fixes: 220ab9bd1ccf: "drm/amdgpu: soc15 enable (v3)" Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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bcf32a23 |
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24-Mar-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove duplicate allowed reg CP_CPF_BUSY_STAT Remove duplicate mmCP_CPF_BUSY_STAT from the allowed registers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c6f3e7cb |
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28-Mar-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/soc15: enable psp block for SRIOV SRIOV can support for loading ucode with PSP block, enable it. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cfd83733 |
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28-Feb-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/soc15: bypass pp block for vf Disable pp block if device is vf. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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480e9150 |
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27-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: drop support for reading some registers The RB harvest registers are not necessary, the driver already exposes this info via the info ioctl. GB_BACKEND_MAP has been deprecated since SI and is not relevant to the RB mapping. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c013cea2 |
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24-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: return cached values for some registers (v2) Required for SR-IOV and saves MMIO transactions. v2: drop cached RB harvest registers Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6e9dc861 |
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22-Mar-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:no cg for soc15 of SRIOV no CG for SRIOV on SOC15 Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b4d6126d |
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21-Mar-2017 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:virt_init_setting invoke is missed! this must be invoked during early init Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f9abe35c |
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23-Mar-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add get_clockgating callback for soc15 (v3) v2: squash register typo fix from Ray v3: fix spelling Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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468842a5 |
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15-Feb-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: disable uvd for sriov disable uvd for sriov temporarily. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f8445307 |
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22-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu:vega10: enable virtual display if set via module option Enable virtual displays if the user has enabled them via the kernel command line. Useful in virtual or headless environments. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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796b6568 |
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28-Feb-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/soc15: enable virtual dce for vf VF need virtual dce, enable it if device is vf. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f1a34465 |
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08-Mar-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/soc15: init virt ops for vf If gpu device is vf, set virt ops so that guest can talk with GPU hypervisor. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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86d3798a |
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28-Feb-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/soc15: bypass PSP for VF Bypass PSP block for VF device. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1b922423 |
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08-Mar-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: impl sriov detection for vega10 Read vega10 hw register to detect if sriov is enabled, and call it before IP blocks setting. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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220ab9bd |
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06-Mar-2017 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: soc15 enable (v3) Add soc15 support and enable all the IPs for vega10. v2: squash in xclk fix v3: disable HDP MGCG Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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