1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include "dm_services.h" 28#include "dc.h" 29 30#include "dcn31/dcn31_init.h" 31#include "dcn35/dcn35_init.h" 32 33#include "resource.h" 34#include "include/irq_service_interface.h" 35#include "dcn35_resource.h" 36#include "dml2/dml2_wrapper.h" 37 38#include "dcn20/dcn20_resource.h" 39#include "dcn30/dcn30_resource.h" 40#include "dcn31/dcn31_resource.h" 41#include "dcn32/dcn32_resource.h" 42 43#include "dcn10/dcn10_ipp.h" 44#include "dcn30/dcn30_hubbub.h" 45#include "dcn31/dcn31_hubbub.h" 46#include "dcn35/dcn35_hubbub.h" 47#include "dcn32/dcn32_mpc.h" 48#include "dcn35/dcn35_hubp.h" 49#include "irq/dcn35/irq_service_dcn35.h" 50#include "dcn35/dcn35_dpp.h" 51#include "dcn35/dcn35_optc.h" 52#include "dcn20/dcn20_hwseq.h" 53#include "dcn30/dcn30_hwseq.h" 54#include "dce110/dce110_hwseq.h" 55#include "dcn35/dcn35_opp.h" 56#include "dcn35/dcn35_dsc.h" 57#include "dcn30/dcn30_vpg.h" 58#include "dcn30/dcn30_afmt.h" 59#include "dcn31/dcn31_dio_link_encoder.h" 60#include "dcn35/dcn35_dio_stream_encoder.h" 61#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 62#include "dcn31/dcn31_hpo_dp_link_encoder.h" 63#include "dcn32/dcn32_hpo_dp_link_encoder.h" 64#include "link.h" 65#include "dcn31/dcn31_apg.h" 66#include "dcn32/dcn32_dio_link_encoder.h" 67#include "dcn31/dcn31_vpg.h" 68#include "dcn31/dcn31_afmt.h" 69#include "dce/dce_clock_source.h" 70#include "dce/dce_audio.h" 71#include "dce/dce_hwseq.h" 72#include "clk_mgr.h" 73#include "virtual/virtual_stream_encoder.h" 74#include "dce110/dce110_resource.h" 75#include "dml/display_mode_vba.h" 76#include "dcn35/dcn35_dccg.h" 77#include "dcn35/dcn35_pg_cntl.h" 78#include "dcn10/dcn10_resource.h" 79#include "dcn31/dcn31_panel_cntl.h" 80#include "dcn35/dcn35_hwseq.h" 81#include "dcn35/dcn35_dio_link_encoder.h" 82#include "dml/dcn31/dcn31_fpu.h" /*todo*/ 83#include "dml/dcn35/dcn35_fpu.h" 84#include "dcn35/dcn35_dwb.h" 85#include "dcn35/dcn35_mmhubbub.h" 86 87#include "dcn/dcn_3_5_0_offset.h" 88#include "dcn/dcn_3_5_0_sh_mask.h" 89#include "nbio/nbio_7_11_0_offset.h" 90#include "mmhub/mmhub_3_3_0_offset.h" 91#include "mmhub/mmhub_3_3_0_sh_mask.h" 92 93#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 94#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 95 96#include "reg_helper.h" 97#include "dce/dmub_abm.h" 98#include "dce/dmub_psr.h" 99#include "dce/dmub_replay.h" 100#include "dce/dce_aux.h" 101#include "dce/dce_i2c.h" 102#include "dml/dcn31/display_mode_vba_31.h" /*temp*/ 103#include "vm_helper.h" 104#include "dcn20/dcn20_vmid.h" 105 106#include "dc_state_priv.h" 107 108#include "link_enc_cfg.h" 109#define DC_LOGGER_INIT(logger) 110 111enum dcn35_clk_src_array_id { 112 DCN35_CLK_SRC_PLL0, 113 DCN35_CLK_SRC_PLL1, 114 DCN35_CLK_SRC_PLL2, 115 DCN35_CLK_SRC_PLL3, 116 DCN35_CLK_SRC_PLL4, 117 DCN35_CLK_SRC_TOTAL 118}; 119 120/* begin ********************* 121 * macros to expend register list macro defined in HW object header file 122 */ 123 124/* DCN */ 125/* TODO awful hack. fixup dcn20_dwb.h */ 126#undef BASE_INNER 127#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 128 129#define BASE(seg) BASE_INNER(seg) 130 131#define SR(reg_name)\ 132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 133 reg ## reg_name 134 135#define SR_ARR(reg_name, id) \ 136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 137 138#define SR_ARR_INIT(reg_name, id, value) \ 139 REG_STRUCT[id].reg_name = value 140 141#define SRI(reg_name, block, id)\ 142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 reg ## block ## id ## _ ## reg_name 144 145#define SRI_ARR(reg_name, block, id)\ 146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 147 reg ## block ## id ## _ ## reg_name 148 149#define SR_ARR_I2C(reg_name, id) \ 150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 151 152#define SRI_ARR_I2C(reg_name, block, id)\ 153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 154 reg ## block ## id ## _ ## reg_name 155 156#define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 158 reg ## block ## id ## _ ## reg_name 159 160#define SRI2(reg_name, block, id)\ 161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 162 reg ## reg_name 163 164#define SRI2_ARR(reg_name, block, id)\ 165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 166 reg ## reg_name 167 168#define SRIR(var_name, reg_name, block, id)\ 169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 170 reg ## block ## id ## _ ## reg_name 171 172#define SRII(reg_name, block, id)\ 173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 174 reg ## block ## id ## _ ## reg_name 175 176#define SRII_ARR_2(reg_name, block, id, inst)\ 177 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180#define SRII_MPC_RMU(reg_name, block, id)\ 181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 reg ## block ## id ## _ ## reg_name 183 184#define SRII_DWB(reg_name, temp_name, block, id)\ 185 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 186 reg ## block ## id ## _ ## temp_name 187 188#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 189 .field_name = reg_name ## __ ## field_name ## post_fix 190 191#define DCCG_SRII(reg_name, block, id)\ 192 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 193 reg ## block ## id ## _ ## reg_name 194 195#define VUPDATE_SRII(reg_name, block, id)\ 196 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 197 reg ## reg_name ## _ ## block ## id 198 199/* NBIO */ 200#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 201 202#define NBIO_BASE(seg) \ 203 NBIO_BASE_INNER(seg) 204 205#define NBIO_SR(reg_name)\ 206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 207 regBIF_BX2_ ## reg_name 208 209#define NBIO_SR_ARR(reg_name, id)\ 210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 211 regBIF_BX2_ ## reg_name 212 213#define bios_regs_init() \ 214 ( \ 215 NBIO_SR(BIOS_SCRATCH_3),\ 216 NBIO_SR(BIOS_SCRATCH_6)\ 217 ) 218 219static struct bios_registers bios_regs; 220 221#define clk_src_regs_init(index, pllid)\ 222 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 223 224static struct dce110_clk_src_regs clk_src_regs[5]; 225 226static const struct dce110_clk_src_shift cs_shift = { 227 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 228}; 229 230static const struct dce110_clk_src_mask cs_mask = { 231 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 232}; 233 234#define abm_regs_init(id)\ 235 ABM_DCN32_REG_LIST_RI(id) 236 237static struct dce_abm_registers abm_regs[4]; 238 239static const struct dce_abm_shift abm_shift = { 240 ABM_MASK_SH_LIST_DCN35(__SHIFT) 241}; 242 243static const struct dce_abm_mask abm_mask = { 244 ABM_MASK_SH_LIST_DCN35(_MASK) 245}; 246 247#define audio_regs_init(id)\ 248 AUD_COMMON_REG_LIST_RI(id) 249 250static struct dce_audio_registers audio_regs[7]; 251 252 253#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 257 258static const struct dce_audio_shift audio_shift = { 259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 260}; 261 262static const struct dce_audio_mask audio_mask = { 263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 264}; 265 266#define vpg_regs_init(id)\ 267 VPG_DCN31_REG_LIST_RI(id) 268 269static struct dcn31_vpg_registers vpg_regs[10]; 270 271static const struct dcn31_vpg_shift vpg_shift = { 272 DCN31_VPG_MASK_SH_LIST(__SHIFT) 273}; 274 275static const struct dcn31_vpg_mask vpg_mask = { 276 DCN31_VPG_MASK_SH_LIST(_MASK) 277}; 278 279#define afmt_regs_init(id)\ 280 AFMT_DCN31_REG_LIST_RI(id) 281 282static struct dcn31_afmt_registers afmt_regs[6]; 283 284static const struct dcn31_afmt_shift afmt_shift = { 285 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 286}; 287 288static const struct dcn31_afmt_mask afmt_mask = { 289 DCN31_AFMT_MASK_SH_LIST(_MASK) 290}; 291 292#define apg_regs_init(id)\ 293 APG_DCN31_REG_LIST_RI(id) 294 295static struct dcn31_apg_registers apg_regs[4]; 296 297static const struct dcn31_apg_shift apg_shift = { 298 DCN31_APG_MASK_SH_LIST(__SHIFT) 299}; 300 301static const struct dcn31_apg_mask apg_mask = { 302 DCN31_APG_MASK_SH_LIST(_MASK) 303}; 304 305#define stream_enc_regs_init(id)\ 306 SE_DCN35_REG_LIST_RI(id) 307 308static struct dcn10_stream_enc_registers stream_enc_regs[5]; 309 310static const struct dcn10_stream_encoder_shift se_shift = { 311 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 312}; 313 314static const struct dcn10_stream_encoder_mask se_mask = { 315 SE_COMMON_MASK_SH_LIST_DCN35(_MASK) 316}; 317 318#define aux_regs_init(id)\ 319 DCN2_AUX_REG_LIST_RI(id) 320 321static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 322 323#define hpd_regs_init(id)\ 324 HPD_REG_LIST_RI(id) 325 326static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 327 328 329static const struct dce110_aux_registers_shift aux_shift = { 330 DCN_AUX_MASK_SH_LIST(__SHIFT) 331}; 332 333static const struct dce110_aux_registers_mask aux_mask = { 334 DCN_AUX_MASK_SH_LIST(_MASK) 335}; 336 337#define link_regs_init(id, phyid)\ 338 ( \ 339 LE_DCN35_REG_LIST_RI(id), \ 340 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 341 ) 342 343static struct dcn10_link_enc_registers link_enc_regs[5]; 344 345static const struct dcn10_link_enc_shift le_shift = { 346 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \ 347 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 348}; 349 350static const struct dcn10_link_enc_mask le_mask = { 351 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \ 352 //DPCS_DCN31_MASK_SH_LIST(_MASK) 353}; 354 355#define hpo_dp_stream_encoder_reg_init(id)\ 356 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 357 358static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 359 360static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 361 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 362}; 363 364static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 365 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 366}; 367 368#define hpo_dp_link_encoder_reg_init(id)\ 369 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 370 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 371 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 372 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 373 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 374 375static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 376 377static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 378 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT) 379}; 380 381static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 382 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) 383}; 384 385#define dpp_regs_init(id)\ 386 DPP_REG_LIST_DCN35_RI(id) 387 388static struct dcn3_dpp_registers dpp_regs[4]; 389 390static const struct dcn35_dpp_shift tf_shift = { 391 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT) 392}; 393 394static const struct dcn35_dpp_mask tf_mask = { 395 DPP_REG_LIST_SH_MASK_DCN35(_MASK) 396}; 397 398#define opp_regs_init(id)\ 399 OPP_REG_LIST_DCN35_RI(id) 400 401static struct dcn35_opp_registers opp_regs[4]; 402 403static const struct dcn35_opp_shift opp_shift = { 404 OPP_MASK_SH_LIST_DCN35(__SHIFT) 405}; 406 407static const struct dcn35_opp_mask opp_mask = { 408 OPP_MASK_SH_LIST_DCN35(_MASK) 409}; 410 411#define aux_engine_regs_init(id)\ 412 ( \ 413 AUX_COMMON_REG_LIST0_RI(id), \ 414 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 415 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 416 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \ 417 ) 418 419static struct dce110_aux_registers aux_engine_regs[5]; 420 421#define dwbc_regs_dcn3_init(id)\ 422 DWBC_COMMON_REG_LIST_DCN30_RI(id) 423 424static struct dcn30_dwbc_registers dwbc35_regs[1]; 425 426static const struct dcn35_dwbc_shift dwbc35_shift = { 427 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 428}; 429 430static const struct dcn35_dwbc_mask dwbc35_mask = { 431 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK) 432}; 433 434#define mcif_wb_regs_dcn3_init(id)\ 435 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) 436 437static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; 438 439static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { 440 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 441}; 442 443static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { 444 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 445}; 446 447#define dsc_regsDCN35_init(id)\ 448 DSC_REG_LIST_DCN20_RI(id) 449 450static struct dcn20_dsc_registers dsc_regs[4]; 451 452static const struct dcn35_dsc_shift dsc_shift = { 453 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT) 454}; 455 456static const struct dcn35_dsc_mask dsc_mask = { 457 DSC_REG_LIST_SH_MASK_DCN35(_MASK) 458}; 459 460static struct dcn30_mpc_registers mpc_regs; 461 462#define dcn_mpc_regs_init() \ 463 MPC_REG_LIST_DCN3_2_RI(0),\ 464 MPC_REG_LIST_DCN3_2_RI(1),\ 465 MPC_REG_LIST_DCN3_2_RI(2),\ 466 MPC_REG_LIST_DCN3_2_RI(3),\ 467 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 468 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 469 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 470 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 471 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 472 473static const struct dcn30_mpc_shift mpc_shift = { 474 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 475}; 476 477static const struct dcn30_mpc_mask mpc_mask = { 478 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 479}; 480 481#define optc_regs_init(id)\ 482 OPTC_COMMON_REG_LIST_DCN3_5_RI(id) 483 484static struct dcn_optc_registers optc_regs[4]; 485 486static const struct dcn_optc_shift optc_shift = { 487 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 488}; 489 490static const struct dcn_optc_mask optc_mask = { 491 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 492}; 493 494#define hubp_regs_init(id)\ 495 HUBP_REG_LIST_DCN30_RI(id) 496 497static struct dcn_hubp2_registers hubp_regs[4]; 498 499 500static const struct dcn35_hubp2_shift hubp_shift = { 501 HUBP_MASK_SH_LIST_DCN35(__SHIFT) 502}; 503 504static const struct dcn35_hubp2_mask hubp_mask = { 505 HUBP_MASK_SH_LIST_DCN35(_MASK) 506}; 507 508static struct dcn_hubbub_registers hubbub_reg; 509 510#define hubbub_reg_init()\ 511 HUBBUB_REG_LIST_DCN35(0) 512 513static const struct dcn_hubbub_shift hubbub_shift = { 514 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT) 515}; 516 517static const struct dcn_hubbub_mask hubbub_mask = { 518 HUBBUB_MASK_SH_LIST_DCN35(_MASK) 519}; 520 521static struct dccg_registers dccg_regs; 522 523#define dccg_regs_init()\ 524 DCCG_REG_LIST_DCN35() 525 526static const struct dccg_shift dccg_shift = { 527 DCCG_MASK_SH_LIST_DCN35(__SHIFT) 528}; 529 530static const struct dccg_mask dccg_mask = { 531 DCCG_MASK_SH_LIST_DCN35(_MASK) 532}; 533 534static struct pg_cntl_registers pg_cntl_regs; 535 536#define pg_cntl_dcn35_regs_init() \ 537 PG_CNTL_REG_LIST_DCN35() 538 539static const struct pg_cntl_shift pg_cntl_shift = { 540 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT) 541}; 542 543static const struct pg_cntl_mask pg_cntl_mask = { 544 PG_CNTL_MASK_SH_LIST_DCN35(_MASK) 545}; 546 547#define SRII2(reg_name_pre, reg_name_post, id)\ 548 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 549 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 550 reg ## reg_name_pre ## id ## _ ## reg_name_post 551 552static struct dce_hwseq_registers hwseq_reg; 553 554#define hwseq_reg_init()\ 555 HWSEQ_DCN35_REG_LIST() 556 557#define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\ 558 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 559 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 560 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 561 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 562 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 563 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 564 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 565 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 566 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 567 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 568 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 569 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 570 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 571 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 572 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 573 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 574 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 575 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 576 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 577 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 578 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 579 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 580 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 581 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 582 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 583 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 584 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 585 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 586 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 587 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 588 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 589 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 590 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 591 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 592 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 593 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 594 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 595 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 596 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 597 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 598 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 599 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 600 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 601 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 602 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 603 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\ 604 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ 605 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ 606 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ 607 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 608 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 609 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 610 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 611 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 612 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ 613 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 614 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 615 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 616 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ 623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 627 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 628 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 629 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 630 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 631 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 632 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ 633 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ 634 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 635 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 636 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 637 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 638 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 639 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 640 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ 641 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ 642 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ 643 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ 644 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh) 645 646static const struct dce_hwseq_shift hwseq_shift = { 647 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT) 648}; 649 650static const struct dce_hwseq_mask hwseq_mask = { 651 HWSEQ_DCN35_MASK_SH_LIST(_MASK) 652}; 653 654#define vmid_regs_init(id)\ 655 DCN20_VMID_REG_LIST_RI(id) 656 657static struct dcn_vmid_registers vmid_regs[16]; 658 659static const struct dcn20_vmid_shift vmid_shifts = { 660 DCN20_VMID_MASK_SH_LIST(__SHIFT) 661}; 662 663static const struct dcn20_vmid_mask vmid_masks = { 664 DCN20_VMID_MASK_SH_LIST(_MASK) 665}; 666 667static const struct resource_caps res_cap_dcn35 = { 668 .num_timing_generator = 4, 669 .num_opp = 4, 670 .num_video_plane = 4, 671 .num_audio = 5, 672 .num_stream_encoder = 5, 673 .num_dig_link_enc = 5, 674 .num_hpo_dp_stream_encoder = 4, 675 .num_hpo_dp_link_encoder = 2, 676 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ 677 .num_dwb = 1, 678 .num_ddc = 5, 679 .num_vmid = 16, 680 .num_mpc_3dlut = 2, 681 .num_dsc = 4, 682}; 683 684static const struct dc_plane_cap plane_cap = { 685 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 686 .per_pixel_alpha = true, 687 688 .pixel_format_support = { 689 .argb8888 = true, 690 .nv12 = true, 691 .fp16 = true, 692 .p010 = true, 693 .ayuv = false, 694 }, 695 696 .max_upscale_factor = { 697 .argb8888 = 16000, 698 .nv12 = 16000, 699 .fp16 = 16000 700 }, 701 702 // 6:1 downscaling ratio: 1000/6 = 166.666 703 .max_downscale_factor = { 704 .argb8888 = 250, 705 .nv12 = 167, 706 .fp16 = 167 707 }, 708 64, 709 64 710}; 711 712static const struct dc_debug_options debug_defaults_drv = { 713 .disable_dmcu = true, 714 .force_abm_enable = false, 715 .timing_trace = false, 716 .clock_trace = true, 717 .disable_pplib_clock_request = false, 718 .pipe_split_policy = MPC_SPLIT_AVOID, 719 .force_single_disp_pipe_split = false, 720 .disable_dcc = DCC_ENABLE, 721 .disable_dpp_power_gate = true, 722 .disable_hubp_power_gate = true, 723 .disable_optc_power_gate = true, /*should the same as above two*/ 724 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/ 725 .disable_clock_gate = false, 726 .disable_dsc_power_gate = true, 727 .vsr_support = true, 728 .performance_trace = false, 729 .max_downscale_src_width = 4096,/*upto true 4k*/ 730 .disable_pplib_wm_range = false, 731 .scl_reset_length10 = true, 732 .sanity_checks = false, 733 .underflow_assert_delay_us = 0xFFFFFFFF, 734 .dwb_fi_phase = -1, // -1 = disable, 735 .dmub_command_table = true, 736 .pstate_enabled = true, 737 .use_max_lb = true, 738 .enable_mem_low_power = { 739 .bits = { 740 .vga = false, 741 .i2c = true, 742 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 743 .dscl = true, 744 .cm = true, 745 .mpc = true, 746 .optc = true, 747 .vpg = true, 748 .afmt = true, 749 } 750 }, 751 .root_clock_optimization = { 752 .bits = { 753 .dpp = true, 754 .dsc = true,/*dscclk and dsc pg*/ 755 .hdmistream = true, 756 .hdmichar = true, 757 .dpstream = true, 758 .symclk32_se = true, 759 .symclk32_le = true, 760 .symclk_fe = true, 761 .physymclk = true, 762 .dpiasymclk = true, 763 } 764 }, 765 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 766 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 767 .minimum_z8_residency_time = 2100, 768 .using_dml2 = true, 769 .support_eDP1_5 = true, 770 .enable_hpo_pg_support = false, 771 .enable_legacy_fast_update = true, 772 .enable_single_display_2to1_odm_policy = false, 773 .disable_idle_power_optimizations = false, 774 .dmcub_emulation = false, 775 .disable_boot_optimizations = false, 776 .disable_unbounded_requesting = false, 777 .disable_mem_low_power = false, 778 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 779 .enable_double_buffered_dsc_pg_support = true, 780 .enable_dp_dig_pixel_rate_div_policy = 1, 781 .disable_z10 = false, 782 .ignore_pg = true, 783 .psp_disabled_wa = true, 784 .ips2_eval_delay_us = 2000, 785 .ips2_entry_delay_us = 800, 786 .disable_dmub_reallow_idle = true, 787 .static_screen_wait_frames = 2, 788}; 789 790static const struct dc_panel_config panel_config_defaults = { 791 .psr = { 792 .disable_psr = false, 793 .disallow_psrsu = false, 794 .disallow_replay = false, 795 }, 796 .ilr = { 797 .optimize_edp_link_rate = true, 798 }, 799}; 800 801static void dcn35_dpp_destroy(struct dpp **dpp) 802{ 803 kfree(TO_DCN20_DPP(*dpp)); 804 *dpp = NULL; 805} 806 807static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) 808{ 809 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 810 bool success = (dpp != NULL); 811 812 if (!success) 813 return NULL; 814 815#undef REG_STRUCT 816#define REG_STRUCT dpp_regs 817 dpp_regs_init(0), 818 dpp_regs_init(1), 819 dpp_regs_init(2), 820 dpp_regs_init(3); 821 822 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, 823 &tf_mask); 824 if (success) { 825 dpp35_set_fgcg( 826 dpp, 827 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); 828 return &dpp->base; 829 } 830 831 BREAK_TO_DEBUGGER(); 832 kfree(dpp); 833 return NULL; 834} 835 836static struct output_pixel_processor *dcn35_opp_create( 837 struct dc_context *ctx, uint32_t inst) 838{ 839 struct dcn20_opp *opp = 840 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 841 842 if (!opp) { 843 BREAK_TO_DEBUGGER(); 844 return NULL; 845 } 846 847#undef REG_STRUCT 848#define REG_STRUCT opp_regs 849 opp_regs_init(0), 850 opp_regs_init(1), 851 opp_regs_init(2), 852 opp_regs_init(3); 853 854 dcn35_opp_construct(opp, ctx, inst, 855 &opp_regs[inst], &opp_shift, &opp_mask); 856 857 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); 858 859 return &opp->base; 860} 861 862static struct dce_aux *dcn31_aux_engine_create( 863 struct dc_context *ctx, 864 uint32_t inst) 865{ 866 struct aux_engine_dce110 *aux_engine = 867 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 868 869 if (!aux_engine) 870 return NULL; 871 872#undef REG_STRUCT 873#define REG_STRUCT aux_engine_regs 874 aux_engine_regs_init(0), 875 aux_engine_regs_init(1), 876 aux_engine_regs_init(2), 877 aux_engine_regs_init(3), 878 aux_engine_regs_init(4); 879 880 dce110_aux_engine_construct(aux_engine, ctx, inst, 881 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 882 &aux_engine_regs[inst], 883 &aux_mask, 884 &aux_shift, 885 ctx->dc->caps.extended_aux_timeout_support); 886 887 return &aux_engine->base; 888} 889 890#define i2c_inst_regs_init(id)\ 891 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 892 893static struct dce_i2c_registers i2c_hw_regs[5]; 894 895static const struct dce_i2c_shift i2c_shifts = { 896 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 897}; 898 899static const struct dce_i2c_mask i2c_masks = { 900 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) 901}; 902 903/* ========================================================== */ 904 905/* 906 * DPIA index | Preferred Encoder | Host Router 907 * 0 | C | 0 908 * 1 | First Available | 0 909 * 2 | D | 1 910 * 3 | First Available | 1 911 */ 912/* ========================================================== */ 913static const enum engine_id dpia_to_preferred_enc_id_table[] = { 914 ENGINE_ID_DIGC, 915 ENGINE_ID_DIGC, 916 ENGINE_ID_DIGD, 917 ENGINE_ID_DIGD 918}; 919 920static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index) 921{ 922 return dpia_to_preferred_enc_id_table[dpia_index]; 923} 924 925static struct dce_i2c_hw *dcn31_i2c_hw_create( 926 struct dc_context *ctx, 927 uint32_t inst) 928{ 929 struct dce_i2c_hw *dce_i2c_hw = 930 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 931 932 if (!dce_i2c_hw) 933 return NULL; 934 935#undef REG_STRUCT 936#define REG_STRUCT i2c_hw_regs 937 i2c_inst_regs_init(1), 938 i2c_inst_regs_init(2), 939 i2c_inst_regs_init(3), 940 i2c_inst_regs_init(4), 941 i2c_inst_regs_init(5); 942 943 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 944 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 945 946 return dce_i2c_hw; 947} 948static struct mpc *dcn35_mpc_create( 949 struct dc_context *ctx, 950 int num_mpcc, 951 int num_rmu) 952{ 953 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 954 955 if (!mpc30) 956 return NULL; 957 958#undef REG_STRUCT 959#define REG_STRUCT mpc_regs 960 dcn_mpc_regs_init(); 961 962 dcn32_mpc_construct(mpc30, ctx, 963 &mpc_regs, 964 &mpc_shift, 965 &mpc_mask, 966 num_mpcc, 967 num_rmu); 968 969 return &mpc30->base; 970} 971 972static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) 973{ 974 int i; 975 976 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 977 GFP_KERNEL); 978 979 if (!hubbub3) 980 return NULL; 981 982#undef REG_STRUCT 983#define REG_STRUCT hubbub_reg 984 hubbub_reg_init(); 985 986#undef REG_STRUCT 987#define REG_STRUCT vmid_regs 988 vmid_regs_init(0), 989 vmid_regs_init(1), 990 vmid_regs_init(2), 991 vmid_regs_init(3), 992 vmid_regs_init(4), 993 vmid_regs_init(5), 994 vmid_regs_init(6), 995 vmid_regs_init(7), 996 vmid_regs_init(8), 997 vmid_regs_init(9), 998 vmid_regs_init(10), 999 vmid_regs_init(11), 1000 vmid_regs_init(12), 1001 vmid_regs_init(13), 1002 vmid_regs_init(14), 1003 vmid_regs_init(15); 1004 1005 hubbub35_construct(hubbub3, ctx, 1006 &hubbub_reg, 1007 &hubbub_shift, 1008 &hubbub_mask, 1009 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/ 1010 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/ 1011 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/); 1012 1013 1014 for (i = 0; i < res_cap_dcn35.num_vmid; i++) { 1015 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1016 1017 vmid->ctx = ctx; 1018 1019 vmid->regs = &vmid_regs[i]; 1020 vmid->shifts = &vmid_shifts; 1021 vmid->masks = &vmid_masks; 1022 } 1023 1024 return &hubbub3->base; 1025} 1026 1027static struct timing_generator *dcn35_timing_generator_create( 1028 struct dc_context *ctx, 1029 uint32_t instance) 1030{ 1031 struct optc *tgn10 = 1032 kzalloc(sizeof(struct optc), GFP_KERNEL); 1033 1034 if (!tgn10) 1035 return NULL; 1036 1037#undef REG_STRUCT 1038#define REG_STRUCT optc_regs 1039 optc_regs_init(0), 1040 optc_regs_init(1), 1041 optc_regs_init(2), 1042 optc_regs_init(3); 1043 1044 tgn10->base.inst = instance; 1045 tgn10->base.ctx = ctx; 1046 1047 tgn10->tg_regs = &optc_regs[instance]; 1048 tgn10->tg_shift = &optc_shift; 1049 tgn10->tg_mask = &optc_mask; 1050 1051 dcn35_timing_generator_init(tgn10); 1052 1053 return &tgn10->base; 1054} 1055 1056static const struct encoder_feature_support link_enc_feature = { 1057 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1058 .max_hdmi_pixel_clock = 600000, 1059 .hdmi_ycbcr420_supported = true, 1060 .dp_ycbcr420_supported = true, 1061 .fec_supported = true, 1062 .flags.bits.IS_HBR2_CAPABLE = true, 1063 .flags.bits.IS_HBR3_CAPABLE = true, 1064 .flags.bits.IS_TPS3_CAPABLE = true, 1065 .flags.bits.IS_TPS4_CAPABLE = true 1066}; 1067 1068static struct link_encoder *dcn35_link_encoder_create( 1069 struct dc_context *ctx, 1070 const struct encoder_init_data *enc_init_data) 1071{ 1072 struct dcn20_link_encoder *enc20 = 1073 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1074 1075 if (!enc20) 1076 return NULL; 1077 1078#undef REG_STRUCT 1079#define REG_STRUCT link_enc_aux_regs 1080 aux_regs_init(0), 1081 aux_regs_init(1), 1082 aux_regs_init(2), 1083 aux_regs_init(3), 1084 aux_regs_init(4); 1085 1086#undef REG_STRUCT 1087#define REG_STRUCT link_enc_hpd_regs 1088 hpd_regs_init(0), 1089 hpd_regs_init(1), 1090 hpd_regs_init(2), 1091 hpd_regs_init(3), 1092 hpd_regs_init(4); 1093 1094#undef REG_STRUCT 1095#define REG_STRUCT link_enc_regs 1096 link_regs_init(0, A), 1097 link_regs_init(1, B), 1098 link_regs_init(2, C), 1099 link_regs_init(3, D), 1100 link_regs_init(4, E); 1101 1102 dcn35_link_encoder_construct(enc20, 1103 enc_init_data, 1104 &link_enc_feature, 1105 &link_enc_regs[enc_init_data->transmitter], 1106 &link_enc_aux_regs[enc_init_data->channel - 1], 1107 &link_enc_hpd_regs[enc_init_data->hpd_source], 1108 &le_shift, 1109 &le_mask); 1110 1111 return &enc20->enc10.base; 1112} 1113 1114/* Create a minimal link encoder object not associated with a particular 1115 * physical connector. 1116 * resource_funcs.link_enc_create_minimal 1117 */ 1118static struct link_encoder *dcn31_link_enc_create_minimal( 1119 struct dc_context *ctx, enum engine_id eng_id) 1120{ 1121 struct dcn20_link_encoder *enc20; 1122 1123 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1124 return NULL; 1125 1126 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1127 if (!enc20) 1128 return NULL; 1129 1130 dcn31_link_encoder_construct_minimal( 1131 enc20, 1132 ctx, 1133 &link_enc_feature, 1134 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1135 eng_id); 1136 1137 return &enc20->enc10.base; 1138} 1139 1140static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1141{ 1142 struct dcn31_panel_cntl *panel_cntl = 1143 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1144 1145 if (!panel_cntl) 1146 return NULL; 1147 1148 dcn31_panel_cntl_construct(panel_cntl, init_data); 1149 1150 return &panel_cntl->base; 1151} 1152 1153static void read_dce_straps( 1154 struct dc_context *ctx, 1155 struct resource_straps *straps) 1156{ 1157 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1158 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1159 1160} 1161 1162static struct audio *dcn31_create_audio( 1163 struct dc_context *ctx, unsigned int inst) 1164{ 1165 1166#undef REG_STRUCT 1167#define REG_STRUCT audio_regs 1168 audio_regs_init(0), 1169 audio_regs_init(1), 1170 audio_regs_init(2), 1171 audio_regs_init(3), 1172 audio_regs_init(4); 1173 audio_regs_init(5); 1174 audio_regs_init(6); 1175 1176 return dce_audio_create(ctx, inst, 1177 &audio_regs[inst], &audio_shift, &audio_mask); 1178} 1179 1180static struct vpg *dcn31_vpg_create( 1181 struct dc_context *ctx, 1182 uint32_t inst) 1183{ 1184 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1185 1186 if (!vpg31) 1187 return NULL; 1188 1189#undef REG_STRUCT 1190#define REG_STRUCT vpg_regs 1191 vpg_regs_init(0), 1192 vpg_regs_init(1), 1193 vpg_regs_init(2), 1194 vpg_regs_init(3), 1195 vpg_regs_init(4), 1196 vpg_regs_init(5), 1197 vpg_regs_init(6), 1198 vpg_regs_init(7), 1199 vpg_regs_init(8), 1200 vpg_regs_init(9); 1201 1202 vpg31_construct(vpg31, ctx, inst, 1203 &vpg_regs[inst], 1204 &vpg_shift, 1205 &vpg_mask); 1206 1207 return &vpg31->base; 1208} 1209 1210static struct afmt *dcn31_afmt_create( 1211 struct dc_context *ctx, 1212 uint32_t inst) 1213{ 1214 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1215 1216 if (!afmt31) 1217 return NULL; 1218 1219#undef REG_STRUCT 1220#define REG_STRUCT afmt_regs 1221 afmt_regs_init(0), 1222 afmt_regs_init(1), 1223 afmt_regs_init(2), 1224 afmt_regs_init(3), 1225 afmt_regs_init(4), 1226 afmt_regs_init(5); 1227 1228 afmt31_construct(afmt31, ctx, inst, 1229 &afmt_regs[inst], 1230 &afmt_shift, 1231 &afmt_mask); 1232 1233 // Light sleep by default, no need to power down here 1234 1235 return &afmt31->base; 1236} 1237 1238static struct apg *dcn31_apg_create( 1239 struct dc_context *ctx, 1240 uint32_t inst) 1241{ 1242 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1243 1244 if (!apg31) 1245 return NULL; 1246 1247#undef REG_STRUCT 1248#define REG_STRUCT apg_regs 1249 apg_regs_init(0), 1250 apg_regs_init(1), 1251 apg_regs_init(2), 1252 apg_regs_init(3); 1253 1254 apg31_construct(apg31, ctx, inst, 1255 &apg_regs[inst], 1256 &apg_shift, 1257 &apg_mask); 1258 1259 return &apg31->base; 1260} 1261 1262static struct stream_encoder *dcn35_stream_encoder_create( 1263 enum engine_id eng_id, 1264 struct dc_context *ctx) 1265{ 1266 struct dcn10_stream_encoder *enc1; 1267 struct vpg *vpg; 1268 struct afmt *afmt; 1269 int vpg_inst; 1270 int afmt_inst; 1271 1272 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1273 if (eng_id <= ENGINE_ID_DIGF) { 1274 vpg_inst = eng_id; 1275 afmt_inst = eng_id; 1276 } else 1277 return NULL; 1278 1279 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1280 vpg = dcn31_vpg_create(ctx, vpg_inst); 1281 afmt = dcn31_afmt_create(ctx, afmt_inst); 1282 1283 if (!enc1 || !vpg || !afmt) { 1284 kfree(enc1); 1285 kfree(vpg); 1286 kfree(afmt); 1287 return NULL; 1288 } 1289 1290#undef REG_STRUCT 1291#define REG_STRUCT stream_enc_regs 1292 stream_enc_regs_init(0), 1293 stream_enc_regs_init(1), 1294 stream_enc_regs_init(2), 1295 stream_enc_regs_init(3), 1296 stream_enc_regs_init(4); 1297 1298 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1299 eng_id, vpg, afmt, 1300 &stream_enc_regs[eng_id], 1301 &se_shift, &se_mask); 1302 1303 return &enc1->base; 1304} 1305 1306static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1307 enum engine_id eng_id, 1308 struct dc_context *ctx) 1309{ 1310 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1311 struct vpg *vpg; 1312 struct apg *apg; 1313 uint32_t hpo_dp_inst; 1314 uint32_t vpg_inst; 1315 uint32_t apg_inst; 1316 1317 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1318 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1319 1320 /* Mapping of VPG register blocks to HPO DP block instance: 1321 * VPG[6] -> HPO_DP[0] 1322 * VPG[7] -> HPO_DP[1] 1323 * VPG[8] -> HPO_DP[2] 1324 * VPG[9] -> HPO_DP[3] 1325 */ 1326 vpg_inst = hpo_dp_inst + 6; 1327 1328 /* Mapping of APG register blocks to HPO DP block instance: 1329 * APG[0] -> HPO_DP[0] 1330 * APG[1] -> HPO_DP[1] 1331 * APG[2] -> HPO_DP[2] 1332 * APG[3] -> HPO_DP[3] 1333 */ 1334 apg_inst = hpo_dp_inst; 1335 1336 /* allocate HPO stream encoder and create VPG sub-block */ 1337 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1338 vpg = dcn31_vpg_create(ctx, vpg_inst); 1339 apg = dcn31_apg_create(ctx, apg_inst); 1340 1341 if (!hpo_dp_enc31 || !vpg || !apg) { 1342 kfree(hpo_dp_enc31); 1343 kfree(vpg); 1344 kfree(apg); 1345 return NULL; 1346 } 1347 1348#undef REG_STRUCT 1349#define REG_STRUCT hpo_dp_stream_enc_regs 1350 hpo_dp_stream_encoder_reg_init(0), 1351 hpo_dp_stream_encoder_reg_init(1), 1352 hpo_dp_stream_encoder_reg_init(2), 1353 hpo_dp_stream_encoder_reg_init(3); 1354 1355 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1356 hpo_dp_inst, eng_id, vpg, apg, 1357 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1358 &hpo_dp_se_shift, &hpo_dp_se_mask); 1359 1360 return &hpo_dp_enc31->base; 1361} 1362 1363static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1364 uint8_t inst, 1365 struct dc_context *ctx) 1366{ 1367 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1368 1369 /* allocate HPO link encoder */ 1370 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1371 1372#undef REG_STRUCT 1373#define REG_STRUCT hpo_dp_link_enc_regs 1374 hpo_dp_link_encoder_reg_init(0), 1375 hpo_dp_link_encoder_reg_init(1); 1376 1377 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1378 &hpo_dp_link_enc_regs[inst], 1379 &hpo_dp_le_shift, &hpo_dp_le_mask); 1380 1381 return &hpo_dp_enc31->base; 1382} 1383 1384static struct dce_hwseq *dcn35_hwseq_create( 1385 struct dc_context *ctx) 1386{ 1387 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1388 1389#undef REG_STRUCT 1390#define REG_STRUCT hwseq_reg 1391 hwseq_reg_init(); 1392 1393 if (hws) { 1394 hws->ctx = ctx; 1395 hws->regs = &hwseq_reg; 1396 hws->shifts = &hwseq_shift; 1397 hws->masks = &hwseq_mask; 1398 } 1399 return hws; 1400} 1401static const struct resource_create_funcs res_create_funcs = { 1402 .read_dce_straps = read_dce_straps, 1403 .create_audio = dcn31_create_audio, 1404 .create_stream_encoder = dcn35_stream_encoder_create, 1405 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1406 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1407 .create_hwseq = dcn35_hwseq_create, 1408}; 1409 1410static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) 1411{ 1412 unsigned int i; 1413 1414 for (i = 0; i < pool->base.stream_enc_count; i++) { 1415 if (pool->base.stream_enc[i] != NULL) { 1416 if (pool->base.stream_enc[i]->vpg != NULL) { 1417 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1418 pool->base.stream_enc[i]->vpg = NULL; 1419 } 1420 if (pool->base.stream_enc[i]->afmt != NULL) { 1421 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1422 pool->base.stream_enc[i]->afmt = NULL; 1423 } 1424 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1425 pool->base.stream_enc[i] = NULL; 1426 } 1427 } 1428 1429 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1430 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1431 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1432 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1433 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1434 } 1435 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1436 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1437 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1438 } 1439 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1440 pool->base.hpo_dp_stream_enc[i] = NULL; 1441 } 1442 } 1443 1444 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1445 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1446 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1447 pool->base.hpo_dp_link_enc[i] = NULL; 1448 } 1449 } 1450 1451 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1452 if (pool->base.dscs[i] != NULL) 1453 dcn20_dsc_destroy(&pool->base.dscs[i]); 1454 } 1455 1456 if (pool->base.mpc != NULL) { 1457 kfree(TO_DCN20_MPC(pool->base.mpc)); 1458 pool->base.mpc = NULL; 1459 } 1460 if (pool->base.hubbub != NULL) { 1461 kfree(pool->base.hubbub); 1462 pool->base.hubbub = NULL; 1463 } 1464 for (i = 0; i < pool->base.pipe_count; i++) { 1465 if (pool->base.dpps[i] != NULL) 1466 dcn35_dpp_destroy(&pool->base.dpps[i]); 1467 1468 if (pool->base.ipps[i] != NULL) 1469 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1470 1471 if (pool->base.hubps[i] != NULL) { 1472 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1473 pool->base.hubps[i] = NULL; 1474 } 1475 1476 if (pool->base.irqs != NULL) { 1477 dal_irq_service_destroy(&pool->base.irqs); 1478 } 1479 } 1480 1481 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1482 if (pool->base.engines[i] != NULL) 1483 dce110_engine_destroy(&pool->base.engines[i]); 1484 if (pool->base.hw_i2cs[i] != NULL) { 1485 kfree(pool->base.hw_i2cs[i]); 1486 pool->base.hw_i2cs[i] = NULL; 1487 } 1488 if (pool->base.sw_i2cs[i] != NULL) { 1489 kfree(pool->base.sw_i2cs[i]); 1490 pool->base.sw_i2cs[i] = NULL; 1491 } 1492 } 1493 1494 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1495 if (pool->base.opps[i] != NULL) 1496 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1497 } 1498 1499 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1500 if (pool->base.timing_generators[i] != NULL) { 1501 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1502 pool->base.timing_generators[i] = NULL; 1503 } 1504 } 1505 1506 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1507 if (pool->base.dwbc[i] != NULL) { 1508 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1509 pool->base.dwbc[i] = NULL; 1510 } 1511 if (pool->base.mcif_wb[i] != NULL) { 1512 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1513 pool->base.mcif_wb[i] = NULL; 1514 } 1515 } 1516 1517 for (i = 0; i < pool->base.audio_count; i++) { 1518 if (pool->base.audios[i]) 1519 dce_aud_destroy(&pool->base.audios[i]); 1520 } 1521 1522 for (i = 0; i < pool->base.clk_src_count; i++) { 1523 if (pool->base.clock_sources[i] != NULL) { 1524 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1525 pool->base.clock_sources[i] = NULL; 1526 } 1527 } 1528 1529 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1530 if (pool->base.mpc_lut[i] != NULL) { 1531 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1532 pool->base.mpc_lut[i] = NULL; 1533 } 1534 if (pool->base.mpc_shaper[i] != NULL) { 1535 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1536 pool->base.mpc_shaper[i] = NULL; 1537 } 1538 } 1539 1540 if (pool->base.dp_clock_source != NULL) { 1541 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1542 pool->base.dp_clock_source = NULL; 1543 } 1544 1545 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1546 if (pool->base.multiple_abms[i] != NULL) 1547 dce_abm_destroy(&pool->base.multiple_abms[i]); 1548 } 1549 1550 if (pool->base.psr != NULL) 1551 dmub_psr_destroy(&pool->base.psr); 1552 1553 if (pool->base.replay != NULL) 1554 dmub_replay_destroy(&pool->base.replay); 1555 1556 if (pool->base.pg_cntl != NULL) 1557 dcn_pg_cntl_destroy(&pool->base.pg_cntl); 1558 1559 if (pool->base.dccg != NULL) 1560 dcn_dccg_destroy(&pool->base.dccg); 1561} 1562 1563static struct hubp *dcn35_hubp_create( 1564 struct dc_context *ctx, 1565 uint32_t inst) 1566{ 1567 struct dcn20_hubp *hubp2 = 1568 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1569 1570 if (!hubp2) 1571 return NULL; 1572 1573#undef REG_STRUCT 1574#define REG_STRUCT hubp_regs 1575 hubp_regs_init(0), 1576 hubp_regs_init(1), 1577 hubp_regs_init(2), 1578 hubp_regs_init(3); 1579 1580 if (hubp35_construct(hubp2, ctx, inst, 1581 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1582 return &hubp2->base; 1583 1584 BREAK_TO_DEBUGGER(); 1585 kfree(hubp2); 1586 return NULL; 1587} 1588 1589static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) 1590{ 1591 dcn35_dwbc_set_fgcg( 1592 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); 1593} 1594 1595static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1596{ 1597 int i; 1598 uint32_t pipe_count = pool->res_cap->num_dwb; 1599 1600 for (i = 0; i < pipe_count; i++) { 1601 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1602 GFP_KERNEL); 1603 1604 if (!dwbc30) { 1605 dm_error("DC: failed to create dwbc30!\n"); 1606 return false; 1607 } 1608 1609#undef REG_STRUCT 1610#define REG_STRUCT dwbc35_regs 1611 dwbc_regs_dcn3_init(0); 1612 1613 dcn35_dwbc_construct(dwbc30, ctx, 1614 &dwbc35_regs[i], 1615 &dwbc35_shift, 1616 &dwbc35_mask, 1617 i); 1618 1619 pool->dwbc[i] = &dwbc30->base; 1620 1621 dcn35_dwbc_init(dwbc30, ctx); 1622 } 1623 return true; 1624} 1625 1626static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, 1627 struct dc_context *ctx) 1628{ 1629 dcn35_mmhubbub_set_fgcg( 1630 mcif_wb30, 1631 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); 1632} 1633 1634static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1635{ 1636 int i; 1637 uint32_t pipe_count = pool->res_cap->num_dwb; 1638 1639 for (i = 0; i < pipe_count; i++) { 1640 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1641 GFP_KERNEL); 1642 1643 if (!mcif_wb30) { 1644 dm_error("DC: failed to create mcif_wb30!\n"); 1645 return false; 1646 } 1647 1648#undef REG_STRUCT 1649#define REG_STRUCT mcif_wb35_regs 1650 mcif_wb_regs_dcn3_init(0); 1651 1652 dcn35_mmhubbub_construct(mcif_wb30, ctx, 1653 &mcif_wb35_regs[i], 1654 &mcif_wb35_shift, 1655 &mcif_wb35_mask, 1656 i); 1657 1658 dcn35_mmhubbub_init(mcif_wb30, ctx); 1659 1660 pool->mcif_wb[i] = &mcif_wb30->base; 1661 } 1662 return true; 1663} 1664 1665static struct display_stream_compressor *dcn35_dsc_create( 1666 struct dc_context *ctx, uint32_t inst) 1667{ 1668 struct dcn20_dsc *dsc = 1669 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1670 1671 if (!dsc) { 1672 BREAK_TO_DEBUGGER(); 1673 return NULL; 1674 } 1675 1676#undef REG_STRUCT 1677#define REG_STRUCT dsc_regs 1678 dsc_regsDCN35_init(0), 1679 dsc_regsDCN35_init(1), 1680 dsc_regsDCN35_init(2), 1681 dsc_regsDCN35_init(3); 1682 1683 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1684 dsc35_set_fgcg(dsc, 1685 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); 1686 return &dsc->base; 1687} 1688 1689static void dcn35_destroy_resource_pool(struct resource_pool **pool) 1690{ 1691 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool); 1692 1693 dcn35_resource_destruct(dcn35_pool); 1694 kfree(dcn35_pool); 1695 *pool = NULL; 1696} 1697 1698static struct clock_source *dcn35_clock_source_create( 1699 struct dc_context *ctx, 1700 struct dc_bios *bios, 1701 enum clock_source_id id, 1702 const struct dce110_clk_src_regs *regs, 1703 bool dp_clk_src) 1704{ 1705 struct dce110_clk_src *clk_src = 1706 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1707 1708 if (!clk_src) 1709 return NULL; 1710 1711 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1712 regs, &cs_shift, &cs_mask)) { 1713 clk_src->base.dp_clk_src = dp_clk_src; 1714 return &clk_src->base; 1715 } 1716 1717 BREAK_TO_DEBUGGER(); 1718 return NULL; 1719} 1720 1721static struct dc_cap_funcs cap_funcs = { 1722 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1723}; 1724 1725static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config) 1726{ 1727 *panel_config = panel_config_defaults; 1728} 1729 1730 1731static bool dcn35_validate_bandwidth(struct dc *dc, 1732 struct dc_state *context, 1733 bool fast_validate) 1734{ 1735 bool out = false; 1736 1737 out = dml2_validate(dc, context, fast_validate); 1738 1739 if (fast_validate) 1740 return out; 1741 1742 DC_FP_START(); 1743 dcn35_decide_zstate_support(dc, context); 1744 DC_FP_END(); 1745 1746 return out; 1747} 1748 1749 1750static struct resource_funcs dcn35_res_pool_funcs = { 1751 .destroy = dcn35_destroy_resource_pool, 1752 .link_enc_create = dcn35_link_encoder_create, 1753 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1754 .link_encs_assign = link_enc_cfg_link_encs_assign, 1755 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1756 .panel_cntl_create = dcn31_panel_cntl_create, 1757 .validate_bandwidth = dcn35_validate_bandwidth, 1758 .calculate_wm_and_dlg = NULL, 1759 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1760 .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu, 1761 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1762 .release_pipe = dcn20_release_pipe, 1763 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1764 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1765 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1766 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1767 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1768 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1769 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1770 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1771 .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, 1772 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1773 .get_panel_config_defaults = dcn35_get_panel_config_defaults, 1774 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia, 1775}; 1776 1777static bool dcn35_resource_construct( 1778 uint8_t num_virtual_links, 1779 struct dc *dc, 1780 struct dcn35_resource_pool *pool) 1781{ 1782 int i; 1783 struct dc_context *ctx = dc->ctx; 1784 struct irq_service_init_data init_data; 1785 1786#undef REG_STRUCT 1787#define REG_STRUCT bios_regs 1788 bios_regs_init(); 1789 1790#undef REG_STRUCT 1791#define REG_STRUCT clk_src_regs 1792 clk_src_regs_init(0, A), 1793 clk_src_regs_init(1, B), 1794 clk_src_regs_init(2, C), 1795 clk_src_regs_init(3, D), 1796 clk_src_regs_init(4, E); 1797 1798#undef REG_STRUCT 1799#define REG_STRUCT abm_regs 1800 abm_regs_init(0), 1801 abm_regs_init(1), 1802 abm_regs_init(2), 1803 abm_regs_init(3); 1804 1805#undef REG_STRUCT 1806#define REG_STRUCT dccg_regs 1807 dccg_regs_init(); 1808 1809 ctx->dc_bios->regs = &bios_regs; 1810 1811 pool->base.res_cap = &res_cap_dcn35; 1812 1813 pool->base.funcs = &dcn35_res_pool_funcs; 1814 1815 /************************************************* 1816 * Resource + asic cap harcoding * 1817 *************************************************/ 1818 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1819 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1820 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1821 dc->caps.max_downscale_ratio = 600; 1822 dc->caps.i2c_speed_in_khz = 100; 1823 dc->caps.i2c_speed_in_khz_hdcp = 100; 1824 dc->caps.max_cursor_size = 256; 1825 dc->caps.min_horizontal_blanking_period = 80; 1826 dc->caps.dmdata_alloc_size = 2048; 1827 dc->caps.max_slave_planes = 2; 1828 dc->caps.max_slave_yuv_planes = 2; 1829 dc->caps.max_slave_rgb_planes = 2; 1830 dc->caps.post_blend_color_processing = true; 1831 dc->caps.force_dp_tps4_for_cp2520 = true; 1832 if (dc->config.forceHBR2CP2520) 1833 dc->caps.force_dp_tps4_for_cp2520 = false; 1834 dc->caps.dp_hpo = true; 1835 dc->caps.dp_hdmi21_pcon_support = true; 1836 1837 dc->caps.edp_dsc_support = true; 1838 dc->caps.extended_aux_timeout_support = true; 1839 dc->caps.dmcub_support = true; 1840 dc->caps.is_apu = true; 1841 dc->caps.seamless_odm = true; 1842 1843 dc->caps.zstate_support = true; 1844 dc->caps.ips_support = true; 1845 dc->caps.max_v_total = (1 << 15) - 1; 1846 1847 /* Color pipeline capabilities */ 1848 dc->caps.color.dpp.dcn_arch = 1; 1849 dc->caps.color.dpp.input_lut_shared = 0; 1850 dc->caps.color.dpp.icsc = 1; 1851 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1852 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1853 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1854 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1855 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1856 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1857 dc->caps.color.dpp.post_csc = 1; 1858 dc->caps.color.dpp.gamma_corr = 1; 1859 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1860 1861 dc->caps.color.dpp.hw_3d_lut = 1; 1862 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 1863 // no OGAM ROM on DCN301 1864 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1865 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1866 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1867 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1868 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1869 dc->caps.color.dpp.ocsc = 0; 1870 1871 dc->caps.color.mpc.gamut_remap = 1; 1872 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1873 dc->caps.color.mpc.ogam_ram = 1; 1874 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1875 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1876 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1877 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1878 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1879 dc->caps.color.mpc.ocsc = 1; 1880 1881 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 1882 * to provide some margin. 1883 * It's expected for furture ASIC to have equal or higher value, in order to 1884 * have determinstic power improvement from generate to genration. 1885 * (i.e., we should not expect new ASIC generation with lower vmin rate) 1886 */ 1887 dc->caps.max_disp_clock_khz_at_vmin = 650000; 1888 1889 /* Use pipe context based otg sync logic */ 1890 dc->config.use_pipe_ctx_sync_logic = true; 1891 1892 /* read VBIOS LTTPR caps */ 1893 { 1894 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1895 enum bp_result bp_query_result; 1896 uint8_t is_vbios_lttpr_enable = 0; 1897 1898 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1899 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1900 } 1901 1902 /* interop bit is implicit */ 1903 { 1904 dc->caps.vbios_lttpr_aware = true; 1905 } 1906 } 1907 1908 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1909 dc->debug = debug_defaults_drv; 1910 /*HW default is to have all the FGCG enabled, SW no need to program them*/ 1911 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; 1912 // Init the vm_helper 1913 if (dc->vm_helper) 1914 vm_helper_init(dc->vm_helper, 16); 1915 1916 /************************************************* 1917 * Create resources * 1918 *************************************************/ 1919 1920 /* Clock Sources for Pixel Clock*/ 1921 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] = 1922 dcn35_clock_source_create(ctx, ctx->dc_bios, 1923 CLOCK_SOURCE_COMBO_PHY_PLL0, 1924 &clk_src_regs[0], false); 1925 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] = 1926 dcn35_clock_source_create(ctx, ctx->dc_bios, 1927 CLOCK_SOURCE_COMBO_PHY_PLL1, 1928 &clk_src_regs[1], false); 1929 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] = 1930 dcn35_clock_source_create(ctx, ctx->dc_bios, 1931 CLOCK_SOURCE_COMBO_PHY_PLL2, 1932 &clk_src_regs[2], false); 1933 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] = 1934 dcn35_clock_source_create(ctx, ctx->dc_bios, 1935 CLOCK_SOURCE_COMBO_PHY_PLL3, 1936 &clk_src_regs[3], false); 1937 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] = 1938 dcn35_clock_source_create(ctx, ctx->dc_bios, 1939 CLOCK_SOURCE_COMBO_PHY_PLL4, 1940 &clk_src_regs[4], false); 1941 1942 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL; 1943 1944 /* todo: not reuse phy_pll registers */ 1945 pool->base.dp_clock_source = 1946 dcn35_clock_source_create(ctx, ctx->dc_bios, 1947 CLOCK_SOURCE_ID_DP_DTO, 1948 &clk_src_regs[0], true); 1949 1950 for (i = 0; i < pool->base.clk_src_count; i++) { 1951 if (pool->base.clock_sources[i] == NULL) { 1952 dm_error("DC: failed to create clock sources!\n"); 1953 BREAK_TO_DEBUGGER(); 1954 goto create_fail; 1955 } 1956 } 1957 /*temp till dml2 fully work without dml1*/ 1958 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); 1959 1960 /* TODO: DCCG */ 1961 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1962 if (pool->base.dccg == NULL) { 1963 dm_error("DC: failed to create dccg!\n"); 1964 BREAK_TO_DEBUGGER(); 1965 goto create_fail; 1966 } 1967 1968#undef REG_STRUCT 1969#define REG_STRUCT pg_cntl_regs 1970 pg_cntl_dcn35_regs_init(); 1971 1972 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); 1973 if (pool->base.pg_cntl == NULL) { 1974 dm_error("DC: failed to create power gate control!\n"); 1975 BREAK_TO_DEBUGGER(); 1976 goto create_fail; 1977 } 1978 1979 /* TODO: IRQ */ 1980 init_data.ctx = dc->ctx; 1981 pool->base.irqs = dal_irq_service_dcn35_create(&init_data); 1982 if (!pool->base.irqs) 1983 goto create_fail; 1984 1985 /* HUBBUB */ 1986 pool->base.hubbub = dcn35_hubbub_create(ctx); 1987 if (pool->base.hubbub == NULL) { 1988 BREAK_TO_DEBUGGER(); 1989 dm_error("DC: failed to create hubbub!\n"); 1990 goto create_fail; 1991 } 1992 1993 /* HUBPs, DPPs, OPPs and TGs */ 1994 for (i = 0; i < pool->base.pipe_count; i++) { 1995 pool->base.hubps[i] = dcn35_hubp_create(ctx, i); 1996 if (pool->base.hubps[i] == NULL) { 1997 BREAK_TO_DEBUGGER(); 1998 dm_error( 1999 "DC: failed to create hubps!\n"); 2000 goto create_fail; 2001 } 2002 2003 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); 2004 if (pool->base.dpps[i] == NULL) { 2005 BREAK_TO_DEBUGGER(); 2006 dm_error( 2007 "DC: failed to create dpps!\n"); 2008 goto create_fail; 2009 } 2010 } 2011 2012 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2013 pool->base.opps[i] = dcn35_opp_create(ctx, i); 2014 if (pool->base.opps[i] == NULL) { 2015 BREAK_TO_DEBUGGER(); 2016 dm_error( 2017 "DC: failed to create output pixel processor!\n"); 2018 goto create_fail; 2019 } 2020 } 2021 2022 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2023 pool->base.timing_generators[i] = dcn35_timing_generator_create( 2024 ctx, i); 2025 if (pool->base.timing_generators[i] == NULL) { 2026 BREAK_TO_DEBUGGER(); 2027 dm_error("DC: failed to create tg!\n"); 2028 goto create_fail; 2029 } 2030 } 2031 pool->base.timing_generator_count = i; 2032 2033 /* PSR */ 2034 pool->base.psr = dmub_psr_create(ctx); 2035 if (pool->base.psr == NULL) { 2036 dm_error("DC: failed to create psr obj!\n"); 2037 BREAK_TO_DEBUGGER(); 2038 goto create_fail; 2039 } 2040 2041 /* Replay */ 2042 pool->base.replay = dmub_replay_create(ctx); 2043 if (pool->base.replay == NULL) { 2044 dm_error("DC: failed to create replay obj!\n"); 2045 BREAK_TO_DEBUGGER(); 2046 goto create_fail; 2047 } 2048 2049 /* ABM */ 2050 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2051 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2052 &abm_regs[i], 2053 &abm_shift, 2054 &abm_mask); 2055 if (pool->base.multiple_abms[i] == NULL) { 2056 dm_error("DC: failed to create abm for pipe %d!\n", i); 2057 BREAK_TO_DEBUGGER(); 2058 goto create_fail; 2059 } 2060 } 2061 2062 /* MPC and DSC */ 2063 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2064 if (pool->base.mpc == NULL) { 2065 BREAK_TO_DEBUGGER(); 2066 dm_error("DC: failed to create mpc!\n"); 2067 goto create_fail; 2068 } 2069 2070 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2071 pool->base.dscs[i] = dcn35_dsc_create(ctx, i); 2072 if (pool->base.dscs[i] == NULL) { 2073 BREAK_TO_DEBUGGER(); 2074 dm_error("DC: failed to create display stream compressor %d!\n", i); 2075 goto create_fail; 2076 } 2077 } 2078 2079 /* DWB and MMHUBBUB */ 2080 if (!dcn35_dwbc_create(ctx, &pool->base)) { 2081 BREAK_TO_DEBUGGER(); 2082 dm_error("DC: failed to create dwbc!\n"); 2083 goto create_fail; 2084 } 2085 2086 if (!dcn35_mmhubbub_create(ctx, &pool->base)) { 2087 BREAK_TO_DEBUGGER(); 2088 dm_error("DC: failed to create mcif_wb!\n"); 2089 goto create_fail; 2090 } 2091 2092 /* AUX and I2C */ 2093 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2094 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2095 if (pool->base.engines[i] == NULL) { 2096 BREAK_TO_DEBUGGER(); 2097 dm_error( 2098 "DC:failed to create aux engine!!\n"); 2099 goto create_fail; 2100 } 2101 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2102 if (pool->base.hw_i2cs[i] == NULL) { 2103 BREAK_TO_DEBUGGER(); 2104 dm_error( 2105 "DC:failed to create hw i2c!!\n"); 2106 goto create_fail; 2107 } 2108 pool->base.sw_i2cs[i] = NULL; 2109 } 2110 2111 /* DCN3.5 has 6 DPIA */ 2112 pool->base.usb4_dpia_count = 4; 2113 if (dc->debug.dpia_debug.bits.disable_dpia) 2114 pool->base.usb4_dpia_count = 0; 2115 2116 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2117 if (!resource_construct(num_virtual_links, dc, &pool->base, 2118 &res_create_funcs)) 2119 goto create_fail; 2120 2121 /* HW Sequencer and Plane caps */ 2122 dcn35_hw_sequencer_construct(dc); 2123 2124 dc->caps.max_planes = pool->base.pipe_count; 2125 2126 for (i = 0; i < dc->caps.max_planes; ++i) 2127 dc->caps.planes[i] = plane_cap; 2128 2129 dc->cap_funcs = cap_funcs; 2130 2131 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 2132 2133 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2134 dc->dml2_options.use_native_pstate_optimization = true; 2135 dc->dml2_options.use_native_soc_bb_construction = true; 2136 dc->dml2_options.minimize_dispclk_using_odm = false; 2137 if (dc->config.EnableMinDispClkODM) 2138 dc->dml2_options.minimize_dispclk_using_odm = true; 2139 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; 2140 2141 dc->dml2_options.callbacks.dc = dc; 2142 dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params; 2143 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2144 dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy; 2145 dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count; 2146 dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count; 2147 dc->dml2_options.callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index; 2148 dc->dml2_options.callbacks.get_odm_slice_index = &resource_get_odm_slice_index; 2149 dc->dml2_options.callbacks.get_opp_head = &resource_get_opp_head; 2150 dc->dml2_options.max_segments_per_hubp = 24; 2151 2152 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ 2153 2154 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2155 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/ 2156 2157 return true; 2158 2159create_fail: 2160 2161 dcn35_resource_destruct(pool); 2162 2163 return false; 2164} 2165 2166struct resource_pool *dcn35_create_resource_pool( 2167 const struct dc_init_data *init_data, 2168 struct dc *dc) 2169{ 2170 struct dcn35_resource_pool *pool = 2171 kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL); 2172 2173 if (!pool) 2174 return NULL; 2175 2176 if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool)) 2177 return &pool->base; 2178 2179 BREAK_TO_DEBUGGER(); 2180 kfree(pool); 2181 return NULL; 2182} 2183