resource/dcn31/dcn31_resource.c

132 #define SRI(reg_name, block, id)\
133 	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 					reg ## block ## id ## _ ## reg_name
136 #define SRI2(reg_name, block, id)\
140 #define SRIR(var_name, reg_name, block, id)\
141 	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 					reg ## block ## id ## _ ## reg_name
144 #define SRII(reg_name, block, id)\
145 	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 					reg ## block ## id ## _ ## reg_name
148 #define SRII_MPC_RMU(reg_name, block, id)\
149 	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 					reg ## block ## id ## _ ## reg_name
152 #define SRII_DWB(reg_name, temp_name, block, id)\
153 	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
154 					reg ## block ## id ## _ ## temp_name
156 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
159 #define DCCG_SRII(reg_name, block, id)\
160 	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 					reg ## block ## id ## _ ## reg_name
163 #define VUPDATE_SRII(reg_name, block, id)\
164 	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
165 					reg ## reg_name ## _ ## block ## id
196 #define CLK_SRI(reg_name, block, inst)\
197 	.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
198 					reg ## block ## _ ## inst ## _ ## reg_name
1229 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1269 	/* Mapping of VPG register blocks to HPO DP block instance:
1277 	/* Mapping of APG register blocks to HPO DP block instance:
1285 	/* allocate HPO stream encoder and create VPG sub-block */