#
18397519 |
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23-Feb-2024 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Add A702 support The A702 is a weird mix of 600 and 700 series.. Perhaps even a testing ground for some A7xx features with good ol' A6xx silicon. It's basically A610 that's been beefed up with some new registers and hw features (like APRIV!), that was then cut back in size, memory bus and some other ways. Add support for it, tested with QCM2290 / RB1. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579752/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
d2bcca0c |
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15-Feb-2024 |
Neil Armstrong <neil.armstrong@linaro.org> |
drm/msm: add support for A750 GPU Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578693/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3d6ab124 |
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21-Jan-2024 |
Luca Weiss <luca@z3ntu.xyz> |
drm/msm/adreno: Add A305B support Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: David Heidelberg <david@ixit.cz> Patchwork: https://patchwork.freedesktop.org/patch/575274/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
8814455a |
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07-Dec-2023 |
Connor Abbott <cwabbott0@gmail.com> |
drm/msm: Refactor UBWC config setting Split up calculating configuration parameters and programming them, so that we can expose them to userspace. Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/571180/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
1f8c29e8 |
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25-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A740 support A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559291/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
9588d2f8 |
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25-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A730 support Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559290/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
af66706a |
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25-Sep-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add skeleton A7xx support A7xx GPUs are - from kernel's POV anyway - basically another generation of A6xx. They build upon the A650/A660_family advancements, skipping some writes (presumably more values are preset correctly on reset), adding some new ones and changing others. One notable difference is the introduction of a second shadow, called BV. To handle this with the current code, allocate it right after the current RPTR shadow. BV handling and .submit are mostly based on Jonathan Marek's work. All A7xx GPUs are assumed to have a GMU. A702 is not an A7xx-class GPU, it's a weird forked A610. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559285/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
90b593ce |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Switch to chip-id for identifying GPU Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549782/
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#
47bd37f9 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move adreno info to config Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549777/
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#
8825f596 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add helper for formating chip-id This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549774/
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#
67133dc0 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Add adreno family Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549773/
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#
75a5227c |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Bring the a630 family together All of these are derivatives of a630. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549770/
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#
c928a05e |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Move speedbin mapping to device table This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549769/
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#
f30a648d |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Allow SoC specific gpu device table entries There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549767/
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#
155668ef |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk to identify cached-coherent support It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549765/
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#
459f9e26 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Use quirk identify hw_apriv Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549764/
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#
f4f1c707 |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove redundant revn param This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549761/
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#
6391030d |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove redundant gmem size param Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549759/
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#
832ee64d |
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27-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Remove GPU name No real need to have marketing names in the kernel. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/549757/
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#
317ab1b9 |
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04-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a690: Remove revn and name These fields are deprecated. But any userspace new enough to support a690 also knows how to identify the GPU based on chip-id. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/545552/
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#
71643600 |
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04-Jul-2023 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Fix warn splat for devices without revn Recently, a WARN_ON() was introduced to ensure that revn is filled before adreno_is_aXYZ is called. This however doesn't work very well when revn is 0 by design (such as for A635). Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Fixes: cc943f43ece7 ("drm/msm/adreno: warn if chip revn is verified before being set") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Patchwork: https://patchwork.freedesktop.org/patch/545554/
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#
b3bcd583 |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542777/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e7fc9398 |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add A610 support A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542779/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
8296ff0a |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Add support for A619_holi A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542775/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
5a903a44 |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/a6xx: Introduce GMU wrapper support Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542766/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
87cc0d0a |
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15-Jun-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Use adreno_is_revn for A690 The adreno_is_revn rework came at the same time as A690 introduction and that resulted in it not covering all cases. Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/542754/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
b263325b |
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12-Jun-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: make adreno_is_a690()'s argument const Change adreno_is_a690() prototype to accept the const struct adreno_gpu pointer instead of a non-const one. This fixes the following warning: In file included from drivers/gpu/drm/msm/msm_drv.c:33: drivers/gpu/drm/msm/adreno/adreno_gpu.h: In function ‘adreno_is_a660_family’: drivers/gpu/drm/msm/adreno/adreno_gpu.h:303:54: warning: passing argument 1 of ‘adreno_is_a690’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 303 | return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); Fixes: 1b90e8f8879c ("drm/msm/adreno: change adreno_is_* functions to accept const argument") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/542138/ Link: https://lore.kernel.org/r/20230612182527.3345786-1-dmitry.baryshkov@linaro.org
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#
1b90e8f8 |
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11-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: change adreno_is_* functions to accept const argument All adreno_is_*() functions do not modify their argument in any way, so they can be changed to accept const struct adreno_gpu pointer. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/531706/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
cc943f43 |
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11-Apr-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: warn if chip revn is verified before being set The commit 010c8bbad2cb ("drm: msm: adreno: Disable preemption on Adreno 510") tried to check GPU's revn before revn being set. Add WARN_ON_ONCE to prevent such bugs from happening again. A separate helper is necessary so that the warning is displayed really just once instead of being displayed for each of comparisons. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/531705/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
5e7665b5 |
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30-May-2023 |
Bjorn Andersson <andersson@kernel.org> |
drm/msm/adreno: Add Adreno A690 support Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
f62ad0f6 |
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14-Feb-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/adreno: split a6xx fault handler into generic and a6xx parts Split the a6xx_fault_handler() into the generic adreno_fault_handler() and platform-specific parts. The adreno_fault_handler() can further be used by a5xx and hopefully by a4xx (at some point). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522722/ Link: https://lore.kernel.org/r/20230214123504.3729522-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
13ef096e |
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02-Jan-2023 |
Konrad Dybcio <konrad.dybcio@linaro.org> |
drm/msm/adreno: Make adreno quirks not overwrite each other So far the adreno quirks have all been assigned with an OR operator, which is problematic, because they were assigned consecutive integer values, which makes checking them with an AND operator kind of no bueno.. Switch to using BIT(n) so that only the quirks that the programmer chose are taken into account when evaluating info->quirks & ADRENO_QUIRK_... Fixes: 370063ee427a ("drm/msm/adreno: Add A540 support") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/516456/ Link: https://lore.kernel.org/r/20230102100201.77286-1-konrad.dybcio@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
822ff993 |
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02-Nov-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm: remove duplicated code from a6xx_create_address_space The function a6xx_create_address_space() is mostly a copy of adreno_iommu_create_address_space() with added quirk setting. Rework these two functions to be a thin wrappers around a common helper. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/509614/ Link: https://lore.kernel.org/r/20221102175449.452283-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
3236130b |
|
02-Nov-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm: move domain allocation into msm_iommu_new() After the msm_iommu instance is created, the IOMMU domain is completely handled inside the msm_iommu code. Move the iommu_domain_alloc() call into the msm_iommu_new() to simplify callers code. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/509615/ Link: https://lore.kernel.org/r/20221102175449.452283-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
36bbfdb8 |
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29-May-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/adreno: Allow larger address space size The restriction to 4G was strictly to work around 64b math bug in some versions of SQE firmware. This appears to be fixed in a650+ SQE fw, so allow a larger address space size on these devices. Also, add a modparam override for debugging and igt. v2: Send the right version of the patch (ie. the one that actually compiles) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/487601/ Link: https://lore.kernel.org/r/20220529180428.2577832-1-robdclark@gmail.com
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#
9bec4399 |
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28-May-2022 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm/adreno: Fix up formatting Leading spaces are not something checkpatch likes, and it says so when they are present. Use tabs consistently to indent function body and unwrap a 83-char-long line, as 100 is cool nowadays. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/487592/ Link: https://lore.kernel.org/r/20220528160353.157870-4-konrad.dybcio@somainline.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
b7616b5c |
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28-May-2022 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm/adreno: Add A619 support Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350), 480 (SM4350) and 750G (SM7225). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/487588/ Link: https://lore.kernel.org/r/20220528160353.157870-2-konrad.dybcio@somainline.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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4bfba716 |
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17-Mar-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm: Add support for pointer params The 64b value field is already suffient to hold a pointer instead of immediate, but we also need a length field. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220317165144.222101-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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f7ddbf55 |
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03-Mar-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm: Add SET_PARAM ioctl It was always expected to have a use for this some day, so we left a placeholder. Now we do. (And I expect another use in the not too distant future when we start allowing userspace to allocate GPU iova.) Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220304005317.776110-3-robdclark@gmail.com
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afab9d91 |
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25-Feb-2022 |
Akhil P Oommen <quic_akhilpo@quicinc.com> |
drm/msm/adreno: Expose speedbin to userspace Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace identify the sku. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Link: https://lore.kernel.org/r/20220226005021.v2.4.I86c32730e08cba9e5c83f02ec17885124d45fa56@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
f98f915b |
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01-Feb-2022 |
Rob Clark <robdclark@chromium.org> |
drm/msm/gpu: Add ctx to get_param() Prep work for next patch. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220201161618.778455-2-robdclark@gmail.com Reviewed-by: Emma Anholt <emma@anholt.net> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
6bf78053 |
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12-Dec-2021 |
Vladimir Lypak <vladimir.lypak@gmail.com> |
drm/msm/a5xx: Add support for Adreno 506 GPU This GPU is found on SoCs such as MSM8953 (650 MHz), SDM450 (600 MHz), SDM632 (725 MHz). Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Link: https://lore.kernel.org/r/20211212160333.980343-1-vladimir.lypak@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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518380cb |
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24-Nov-2021 |
Akhil P Oommen <quic_akhilpo@quicinc.com> |
drm/msm/a6xx: Capture gmu log in devcoredump Capture gmu log in coredump to enhance debugging. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20211124214151.1427022-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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083cc3a4 |
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07-Aug-2021 |
Rob Clark <robdclark@chromium.org> |
drm/msm: Add adreno_is_a640_family() Combine adreno_is_a640() and adreno_is_a680(). Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210807163019.379003-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
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840d10b6 |
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24-Jul-2021 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
drm: msm: Add 680 gpu to the adreno gpu list This patch adds a Adreno 680 entry to the gpulist. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210725032002.3961691-1-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
192f4ee3 |
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29-Jul-2021 |
Akhil P Oommen <akhilpo@codeaurora.org> |
drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu This patch adds support for the gpu found in the Snapdragon 7c Gen 3 compute platform. This gpu is similar to the exisiting a660 gpu with minor delta in the programing sequence. As the Adreno GPUs are moving away from a numeric chipid based naming scheme to a string, it was decided to use 0x06030500 as the chip id of this gpu to communicate to the userspace driver. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.3.I610377db0934b6b7deda532ec2bf786a02c38c01@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
27514ce2 |
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29-Jul-2021 |
Akhil P Oommen <akhilpo@codeaurora.org> |
drm/msm/a6xx: Use rev to identify SKU Use rev instead of revn to identify the SKU. This is in preparation to the introduction of 7c3 gpu which won't have a revn. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210730011945.v4.2.I286ef007fcadd9e6ee3b2c0ad948f990735f9610@changeid Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
f6d62d09 |
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08-Jun-2021 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add support for Adreno 660 GPU Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table, updated a6xx_ucode_check_version check. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-6-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
1d832ab3 |
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13-Jan-2021 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> |
drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs The Adreno 508/509/512 GPUs are stripped versions of the Adreno 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and SDA variants; these SoCs are usually provided with ZAP firmwares, but they have no available GPMU. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Tested-by: Martin Botka <martin.botka1@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
45596f25 |
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11-Jan-2021 |
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> |
drm/msm/a6xx: Create an A6XX GPU specific address space A6XX GPUs have support for last level cache(LLC) also known as system cache and need to set the bus attributes to use it. Currently we use a generic adreno iommu address space implementation which are also used by older GPU generations which do not have LLC and might introduce issues accidentally and is not clean in a way that anymore additions of GPUs supporting LLC would have to be guarded under ifdefs. So keep the generic code separate and make the address space creation A6XX specific. We also have a helper to set the llc attributes so that if the newer GPU generations do support them, we can use it instead of open coding domain attribute setting for each GPU. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
00fd44a1 |
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04-Jan-2021 |
Konrad Dybcio <konrad.dybcio@somainline.org> |
drm/msm: Only enable A6xx LLCC code on A6xx Using this code on A5xx (and probably older too) causes a smmu bug. Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
3f7759e7 |
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30-Dec-2020 |
Iskren Chernev <iskren.chernev@gmail.com> |
drm/msm: Add modparam to allow vram carveout Using the GPU with a VRAM Carveout is a security vulnerability. Nevertheless it is sometimes required, especially when no IOMMU implementation is available for a certain platform. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
2fb7487a |
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14-Sep-2020 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Get rid of the REG_ADRENO offsets As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
15eb9ad0 |
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17-Aug-2020 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Drop context arg to gpu->submit() Now that we can get the ctx from the submitqueue, the extra arg is redundant. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [split out of previous patch to reduce churny noise] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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#
6f7cd6e4 |
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11-Aug-2020 |
Rob Clark <robdclark@chromium.org> |
drm/msm/a6xx: add module param to enable debugbus snapshot For production devices, the debugbus sections will typically be fused off and empty in the gpu device coredump. But since this may contain data like cache contents, don't capture it by default. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
66ffb915 |
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10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add A640/A650 hwcg Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
b1c53a2a |
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10-Jul-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: hwcg tables in gpulist This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
ccac7ce3 |
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22-May-2020 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Refactor address space initialization Refactor how address space initialization works. Instead of having the address space function create the MMU object (and thus require separate but equal functions for gpummu and iommu) use a single function and pass the MMU struct in. Make the generic code cleaner by using target specific functions to create the address space so a2xx can do its own thing in its own space. For all the other targets use a generic helper to initialize IOMMU but leave the door open for newer targets to use customization if they need it. Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> [squash in rebase fixups] Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
dc0fa5eb |
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09-May-2020 |
Shawn Guo <shawn.guo@linaro.org> |
drm/msm/a4xx: add adreno a405 support It adds support for adreno a405 found on MSM8939. The adreno_is_a430() check in adreno_submit() needs an extension to cover a405. The downstream driver suggests it should cover the whole a4xx generation. That's why it gets changed to adreno_is_a4xx(), while a420 is not tested though. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
a83366ef |
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23-Apr-2020 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/a6xx: add A640/A650 to gpulist Add Adreno 640 and 650 GPU info to the gpulist. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e37b624d |
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30-Dec-2019 |
Wambui Karuga <wambui.karugax@gmail.com> |
drm/msm: use BUG_ON macro for debugging. As the if statement only checks for the value of the offset_name variable, it can be replaced by the more conscise BUG_ON macro for error reporting. Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e812744c |
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03-Dec-2019 |
Sharat Masetty <smasetty@codeaurora.org> |
drm: msm: a6xx: Add support for A618 This patch adds support for enabling Graphics Bus Interface(GBIF) used in multiple A6xx series chipets. Also makes changes to the PDC/RSC sequencing specifically required for A618. This is needed for proper interfacing with RPMH. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
e20c9284 |
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31-Oct-2019 |
AngeloGioacchino Del Regno <kholk11@gmail.com> |
drm/msm/adreno: Add support for Adreno 510 GPU The Adreno 510 GPU is a stripped version of the Adreno 5xx, found in low-end SoCs like 8x56 and 8x76, which has 256K of GMEM, with no GPMU nor ZAP. Also, since the Adreno 5xx part of this driver seems to be developed with high-end Adreno GPUs in mind, and since this is a lower end one, add a comment making clear which GPUs which support is not implemented yet is not using the GPMU related hw init code, so that future developers will not go crazy with that. By the way, the lower end Adreno GPUs with no GPMU are: A505/A506/A510 (usually no ZAP firmware) A508/A509/A512 (usually with ZAP firmware) Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
26c0b26d |
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23-Aug-2019 |
Brian Masney <masneyb@onstation.org> |
drm/msm/gpu: add ocmem init/cleanup functions The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support that was missing upstream. Add two new functions (adreno_gpu_ocmem_init and adreno_gpu_ocmem_cleanup) that removes some duplicated code. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Tested-by: Gabriel Francisco <frc.gabrielgmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
caab277b |
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02-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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370063ee |
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11-Jun-2019 |
Jeffrey Hugo <jeffrey.l.hugo@gmail.com> |
drm/msm/adreno: Add A540 support The A540 is a derivative of the A530, and is found in the MSM8998 SoC. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
a9e2559c |
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19-Apr-2019 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Move zap shader loading to adreno a5xx and a6xx both share (mostly) the same code to load the zap shader and bring the GPU out of secure mode. Move the formerly 5xx specific code to adreno to make it available for a6xx too. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
21af872c |
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21-Nov-2018 |
Jonathan Marek <jonathan@marek.ca> |
drm/msm/adreno: add a2xx derived from the a3xx driver and tested on the following hardware: imx51-zii-rdu1 (a200 with 128kb gmem) imx53-qsrb (a200) msm8060-tenderloin (a220) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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983674e2 |
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02-Nov-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Move gpu_poll_timeout() to adreno_gpu.h The gpu_poll_timeout() function can be useful to multiple targets so mvoe it into adreno_gpu.h from the a5xx code. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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4b565ca5 |
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06-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Add A6XX device support Add support for the A6XX family of Adreno GPUs. The biggest addition is the GMU (Graphics Management Unit) which takes over most of the power management of the GPU itself but in a ironic twist of fate needs a goodly amount of management itself. Add support for the A6XX core code, the GMU and the HFI (hardware firmware interface) queue that the CPU uses to communicate with the GMU. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
2c087a33 |
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06-Aug-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Load the firmware before bringing up the hardware Failure to load firmware is the primary reason to fail adreno_load_gpu(). Try to load it first before going into the hardware initialization code and unwinding it. This is important for a6xx because the GMU gets loaded from the runtime power code and it is more costly to fail in that path because of missing firmware. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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50f8d218 |
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24-Jul-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Add a5xx specific registers for the GPU state HLSQ, SP and TP registers are only accessible from a special aperture and to make matters worse the aperture is blocked from the CPU on targets that can support secure rendering. Luckily the GPU hardware has its own purpose built register dumper that can access the registers from the aperture. Add a5xx specific code to program the crashdumper and retrieve the wayward registers and dump them for the crash state. Also, remove a block of registers the regular CPU accessible list that aren't useful for debug which helps reduce the size of the crash state file by a goodly amount. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
c0fec7f5 |
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24-Jul-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Capture the GPU state on a GPU hang Capture the GPU state on a GPU hang and store it for later playback via the devcoredump facility. Only one crash state is stored at a time on the assumption that the first hang is usually the most interesting. The existing crash state can be cleared after capturing it and then a new one will be captured on the next hang. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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4f776f45 |
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24-Jul-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Convert the GPU show function to use the GPU state Convert the existing GPU show function to use the GPU state to dump the information rather than reading it directly from the hardware. This will require an additional step to capture the state before dumping it for the existing nodes but it will greatly facilitate reusing the same code for dumping a previously captured state from a GPU hang. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
e00e473d |
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24-Jul-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Capture the state of the GPU Add the infrastructure to capture the current state of the GPU and store it in memory so that it can be dumped later. For now grab the same basic ringbuffer information and registers that are provided by the debugfs 'gpu' node but obviously this should be extended to capture a much larger set of GPU information. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
64709686 |
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07-May-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Increase the pm runtime autosuspend for 5xx Experimentation shows that resuming power quickly after suspending ends up forcing a system hang for unknown reasons on 5xx targets. To avoid cycling the power too much (especially during init) turn up the autosuspend time for a5xx to 250ms and use pm_runtime_put_autosuspend() when applicable. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
9de43e79 |
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01-Feb-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Use generic function to load firmware to a buffer object Move a5xx specific code to load firmware into a buffer object to the generic Adreno code. This will come in useful for future targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
c5e3548c |
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01-Feb-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Define a list of firmware files to load per target The number and type of firmware files required differs for each target. Instead of using a fixed struct member for each possible firmware file use a generic list of files that should be loaded on boot. Use some semi-target specific enums to help each target find the appropriate firmware(s) that it needs to load. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
f306953f |
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22-Jan-2018 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Rename gpmufw to powerfw The power management device on the a5xx cores is known as the GPMU (Graphics Power Management Unit). On a6xx cores the device was expanded and renamed as the GMU (Graphics Management Unit). Rename the 'gpmufw' name struct adreno_info as 'powerfw' to avoid confusion. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
999ae6ed |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/adreno: Move clock parsing to adreno_gpu_init() Move the clock parsing to adreno_gpu_init() to allow for target specific probing and manipulation of the clock tables. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
1babd706 |
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21-Nov-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm/gpu: Remove unused bus scaling code Remove the downstream bus scaling code. It isn't needed for for compatibility with a downstream or vendor kernel. Get it out of the way to clear space for devfreq support. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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b1fc2839 |
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20-Oct-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Implement preemption for A5XX targets Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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f97decac |
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20-Oct-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Support multiple ringbuffers Add the infrastructure to support the idea of multiple ringbuffers. Assign each ringbuffer an id and use that as an index for the various ring specific operations. The biggest delta is to support legacy fences. Each fence gets its own sequence number but the legacy functions expect to use a unique integer. To handle this we return a unique identifier for each submission but map it to a specific ring/sequence under the covers. Newer users use a dma_fence pointer anyway so they don't care about the actual sequence ID or ring. The actual mechanics for multiple ringbuffers are very target specific so this code just allows for the possibility but still only defines one ringbuffer for each target family. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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cd414f3d |
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20-Oct-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Move memptrs to msm_gpu When we move to multiple ringbuffers we're going to store the data in the memptrs on a per-ring basis. In order to prepare for that move the current memptrs from the adreno namespace into msm_gpu. This is way cleaner and immediately lets us kill off some sub functions so there is much less cost later when we do move to per-ring structs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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2c41ef1b |
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16-Oct-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: deal with linux-firmware fw paths When firmware was added to linux-firmware, it was put in a qcom sub- directory, unlike what we'd been using before. For a300_pfp.fw and a300_pm4.fw symlinks were created, but we'd prefer not to have to do this in the future. So add support to look in both places when loading firmware. Signed-off-by: Rob Clark <robdclark@gmail.com>
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e8f3de96 |
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16-Oct-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: split out helper to load fw Prep work for the next patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
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42a105e9 |
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08-May-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Remove memptrs->wptr memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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7c65817e |
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17-May-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Enable zap shader for A5XX The A5XX GPU powers on in "secure" mode. In secure mode the GPU can only render to buffers that are marked as secure and inaccessible to the kernel and user through a series of hardware protections. In practice secure mode is used to draw things like a UI on a secure video frame. In order to switch out of secure mode the GPU executes a special shader that clears out the GMEM and other sensitve registers and then writes a register. Because the kernel can't be trusted the shader binary is signed and verified and programmed by the secure world. To do this we need to read the MDT header and the segments from the firmware location and put them in memory and present them for approval. For targets without secure support there is an out: if the secure world doesn't support secure then there are no hardware protections and we can freely write the SECVID_TRUST register from the CPU. We don't have 100% confidence that we can query the secure capabilities at run time but we have enough calls that need to go right to give us some confidence that we're at least doing something useful. Of course if we guess wrong you trigger a permissions violation which usually ends up in a system crash but thats a problem that shows up immediately. [v2: use child device per Bjorn] [v3: use generic MDT loader per Bjorn] [v4: use managed dma functions and ifdefs for the MDT loader] [v5: Add depends for QCOM_MDT_LOADER] Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [robclark: fix Kconfig to use select instead of depends + #if IS_ENABLED()] Signed-off-by: Rob Clark <robdclark@gmail.com>
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bf5af4ae |
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07-Mar-2017 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Hard code the GPU "slow frequency" Some A3XX and A4XX GPU targets required that the GPU clock be programmed to a non zero value when it was disabled so 27Mhz was chosen as the "invalid" frequency. Even though newer targets do not have the same clock restrictions we still write 27Mhz on clock disable and expect the clock subsystem to round down to zero. For unknown reasons even though the slow clock speed is always 27Mhz and it isn't actually a functional level the legacy device tree frequency tables always defined it and then did gymnastics to work around it. Instead of playing the same silly games just hard code the "slow" clock speed in the code as 27MHz and save ourselves a bit of infrastructure. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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4e09b95d |
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30-Jan-2017 |
Rob Clark <robdclark@gmail.com> |
drm/msm: drop quirks binding This was never documented or used in upstream dtb. It is used by downstream bindings from android device kernels. But the quirks are a property of the gpu revision, and as such are redundant to be listed separately in dt. Instead, move the quirks to the device table. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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2401a008 |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Add support for the GPMU Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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b5f103ab |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Add A5XX target support Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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05b9401b |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7 Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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fb039981 |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: Add adreno_gpu_write64() Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and writes/reads from that register will be quietly dropped. This can be immediately put in place for the ringbuffer base and the RPTR address. Both writes are converted to use adreno_gpu_write64() with their respective high and low registers and the high register appropriately marked as SKIP for both 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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c4a8d475 |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Return error on hw_init failure When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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bcc188b7 |
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28-Nov-2016 |
Jordan Crouse <jcrouse@codeaurora.org> |
drm/msm: gpu: Cut down the list of "generic" registers to the ones we use There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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78babc16 |
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10-Nov-2016 |
Rob Clark <robdclark@gmail.com> |
drm/msm: convert iova to 64b For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark <robdclark@gmail.com>
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a5725ab0 |
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22-Oct-2016 |
Baoyou Xie <baoyou.xie@linaro.org> |
drm/msm/adreno: move function declarations to header file We get 2 warnings when building kernel with W=1: drivers/gpu/drm/msm/adreno/a3xx_gpu.c:535:17: warning: no previous prototype for 'a3xx_gpu_init' [-Wmissing-prototypes] drivers/gpu/drm/msm/adreno/a4xx_gpu.c:624:17: warning: no previous prototype for 'a4xx_gpu_init' [-Wmissing-prototypes] In fact, both functions are declared in drivers/gpu/drm/msm/adreno/adreno_device.c, but should be declared in a header file. So this patch moves both function declarations to drivers/gpu/drm/msm/adreno/adreno_gpu.h. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1477127865-9381-1-git-send-email-baoyou.xie@linaro.org
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1193c3bc |
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03-May-2016 |
Rob Clark <robdclark@gmail.com> |
drm/msm: drop return from gpu->submit() At this point, there is nothing left to fail. And submit already has a fence assigned and is added to the submit_list. Any problems from here on out are asynchronous (ie. hangcheck/recovery). Signed-off-by: Rob Clark <robdclark@gmail.com>
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6c77d1ab |
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22-Feb-2016 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add timestamp param We need this for GL_TIMESTAMP queries. Note: currently only supported on a4xx.. a3xx doesn't have this always-on counter. I think we could emulate it with the one CP counter that is available, but for now it is of limited usefulness on a3xx (since we can't seem to do time-elapsed queries in any sane way with the existing firmware on a3xx, and if you are trying to do profiling on a tiler you want time-elapsed). We can add that later if it becomes useful. Signed-off-by: Rob Clark <robdclark@gmail.com>
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357ff00b |
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18-Feb-2016 |
Craig Stout <cstout@chromium.org> |
drm/msm/adreno: support for adreno 430. Signed-off-by: Craig Stout <cstout@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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de558cd2 |
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06-May-2015 |
Rob Clark <robdclark@gmail.com> |
drm/msm: adreno a306 support As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark <robdclark@gmail.com>
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6490ad47 |
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04-Jun-2015 |
Rob Clark <robdclark@gmail.com> |
drm/msm: clarify downstream bus scaling A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark <robdclark@gmail.com>
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26716185 |
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19-Apr-2015 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: dump scratch regs and other info on hang Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark <robdclark@gmail.com>
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23bd62fd |
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08-Sep-2014 |
Aravind Ganesan <aravindg@codeaurora.org> |
drm/msm: a4xx support for msm-drm Added a4xx GPU support. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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91b74e97 |
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08-Sep-2014 |
Aravind Ganesan <aravindg@codeaurora.org> |
drm/msm: Handle register offset differences between a3xx and a4xx Register offsets have changed between a3xx and a4xx GPUs. To be able access these registers in common code, we create a lookup table, and set of read-write APIs to access the register through the lookup table. Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org> [robclark: remove REG_ADRENO_UNDEFINED, just use zero, and minor tweaks for latest generated headers] Signed-off-by: Rob Clark <robdclark@gmail.com>
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3bcefb04 |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: push dump/show stuff to base class Add ptr to list of interesting registers to 'struct adreno_gpu' and use that to move most of the debugfs show and register dump bits down into adreno_gpu. This will avoid duplication as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
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3526e9fb |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: bit of init refactoring Push a few bits down into adreno_gpu so they won't have to be duplicated as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
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e2550b7a |
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05-Sep-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm/adreno: move decision about what gpu to to load Move this into into adreno_device, and decide based on gpu revision rather than just assuming a3xx. Signed-off-by: Rob Clark <robdclark@gmail.com>
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0963756f |
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11-Jan-2014 |
Rob Clark <robdclark@gmail.com> |
drm/msm: spin helper Helper macro to simplify places where we need to poll with timeout waiting for gpu. Signed-off-by: Rob Clark <robdclark@gmail.com>
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5b6ef08e |
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22-Dec-2013 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add hang_debug module param msm.hang_debug=y will dump out current register values if the gpu locks up, for easier debugging. Signed-off-by: Rob Clark <robdclark@gmail.com>
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55459968 |
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05-Dec-2013 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add a330/apq8x74 Add support for adreno 330. Not too much different, just a few differences in initial configuration plus setting OCMEM base. Userspace support is already in upstream mesa. Note that the existing DT code is simply using the bindings from downstream android kernel, to simplify porting of this driver to existing devices. These do not constitute any committed/stable DT ABI. The addition of proper DT bindings will be a subsequent patch, at which point (as best as possible) I will try to support either upstream bindings or what is found in downstream android kernel, so that existing device DT files can be used. Signed-off-by: Rob Clark <robdclark@gmail.com>
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bf2b33af |
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15-Nov-2013 |
Rob Clark <robdclark@gmail.com> |
drm/msm: fix bus scaling This got a bit broken with original patches when re-arranging things to move dependencies on mach-msm inside #ifndef OF. Signed-off-by: Rob Clark <robdclark@gmail.com>
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bd6f82d8 |
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24-Aug-2013 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add basic hangcheck/recovery mechanism A basic, no-frills recovery mechanism in case the gpu gets wedged. We could try to be a bit more fancy and restart the next submit after the one that got wedged, but for now keep it simple. This is enough to recover things if, for example, the gpu hangs mid way through a piglit run. Signed-off-by: Rob Clark <robdclark@gmail.com>
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7198e6b0 |
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18-Jul-2013 |
Rob Clark <robdclark@gmail.com> |
drm/msm: add a3xx gpu support Add initial support for a3xx 3d core. So far, with hardware that I've seen to date, we can have: + zero, one, or two z180 2d cores + a3xx or a2xx 3d core, which share a common CP (the firmware for the CP seems to implement some different PM4 packet types but the basics of cmdstream submission are the same) Which means that the eventual complete "class" hierarchy, once support for all past and present hw is in place, becomes: + msm_gpu + adreno_gpu + a3xx_gpu + a2xx_gpu + z180_gpu This commit splits out the parts that will eventually be common between a2xx/a3xx into adreno_gpu, and the parts that are even common to z180 into msm_gpu. Note that there is no cmdstream validation required. All memory access from the GPU is via IOMMU/MMU. So as long as you don't map silly things to the GPU, there isn't much damage that the GPU can do. Signed-off-by: Rob Clark <robdclark@gmail.com>
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