Searched refs:reg_offset (Results 151 - 175 of 374) sorted by relevance

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/linux-master/sound/soc/sof/amd/
H A Dacp-pcm.c40 platform_params->phy_addr = stream->reg_offset;
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmt792x_mac.c39 u32 val, reg_offset; local
55 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
58 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset);
59 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset);
/linux-master/drivers/platform/x86/
H A Dpmc_atom.c206 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) argument
208 return readl(pmc->regmap + reg_offset);
211 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) argument
213 writel(val, pmc->regmap + reg_offset);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.h85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
168 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
H A Dgfx_v7_0.c993 u32 reg_offset, split_equal_to_row_size; local
1012 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1013 tile[reg_offset] = 0;
1014 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1015 macrotile[reg_offset] = 0;
1179 for (reg_offset
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H A Damdgpu_amdkfd_gfx_v9.h102 uint32_t *reg_offset,
H A Dnbio_v7_7.c34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
H A Dnbio_v6_1.c59 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
61 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
281 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
/linux-master/drivers/platform/x86/amd/pmf/
H A Dcore.c160 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) argument
162 return ioread32(dev->regbase + reg_offset);
165 static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val) argument
167 iowrite32(val, dev->regbase + reg_offset);
/linux-master/drivers/input/touchscreen/
H A Dedt-ft5x06.c101 int reg_offset; member in struct:edt_reg_addr
592 if (reg_addr->reg_offset != NO_REGISTER)
593 regmap_write(regmap, reg_addr->reg_offset, tsdata->offset);
1001 if (reg_addr->reg_offset != NO_REGISTER)
1002 regmap_write(regmap, reg_addr->reg_offset, val);
1029 if (reg_addr->reg_offset != NO_REGISTER)
1030 regmap_read(regmap, reg_addr->reg_offset, &tsdata->offset);
1079 reg_addr->reg_offset = WORK_REGISTER_OFFSET;
1092 reg_addr->reg_offset = M09_REGISTER_OFFSET;
1103 reg_addr->reg_offset
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/linux-master/drivers/net/wireless/ath/ath9k/
H A Dar9003_hw.c1102 unsigned int dbg_reg, reg_offset; local
1107 reg_offset = queue * 5;
1110 reg_offset = (queue - 6) * 5;
1117 dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;
1136 unsigned int reg_offset; local
1150 reg_offset = i * 5;
1153 reg_offset = (i - 6) * 5;
1156 dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;
/linux-master/drivers/base/regmap/
H A Dregmap-irq.c211 unsigned int reg = irq_data->reg_offset / map->reg_stride;
241 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
282 d->wake_buf[irq_data->reg_offset / map->reg_stride]
287 d->wake_buf[irq_data->reg_offset / map->reg_stride]
497 if (data->status_buf[chip->irqs[i].reg_offset /
649 if (chip->irqs[i].reg_offset % map->reg_stride)
651 if (chip->irqs[i].reg_offset / map->reg_stride >=
757 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
/linux-master/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_mbox_common.c67 reg_msg->reg_offset = reg;
92 reg_msg->reg_offset = reg;
/linux-master/drivers/net/ethernet/8390/
H A Dhydra.c31 #define EI_SHIFT(x) (ei_local->reg_offset[x])
161 ei_status.reg_offset = hydra_offsets;
/linux-master/drivers/perf/hisilicon/
H A Dhisi_pcie_pmu.c190 static u32 hisi_pcie_pmu_readl(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, argument
193 u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);
198 static void hisi_pcie_pmu_writel(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u32 val) argument
200 u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);
205 static u64 hisi_pcie_pmu_readq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx) argument
207 u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);
212 static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset, u32 idx, u64 val) argument
214 u32 offset = hisi_pcie_pmu_get_offset(reg_offset, idx);
/linux-master/drivers/crypto/hisilicon/
H A Ddebugfs.c119 .reg_offset = QM_DFX_BASE,
122 .reg_offset = QM_DFX_STATE1,
125 .reg_offset = QM_DFX_STATE2,
128 .reg_offset = QM_DFX_COMMON,
835 diff_regs[i].reg_offset = cregs[i].reg_offset;
843 base_offset = diff_regs[i].reg_offset +
988 base_offset = dregs[i].reg_offset + j * QM_DFX_REGS_LEN;
/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-cti-core.c345 int reg_offset; local
369 reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :
390 cti_write_single_reg(drvdata, reg_offset, reg_value);
440 u32 reg_offset; local
454 reg_offset = CTIAPPSET;
460 reg_offset = CTIAPPCLEAR;
466 reg_offset = CTIAPPPULSE;
475 cti_write_single_reg(drvdata, reg_offset, reg_value);
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_sriov.c494 u32 reg_offset, vf_shift, vfre; local
528 reg_offset = vf / 32;
531 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
536 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre);
836 u32 reg_offset, vf_shift; local
839 reg_offset = vf / 32;
841 reg_cur_tx = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
842 reg_cur_rx = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
871 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg_req_tx);
873 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg_req_r
881 u32 reg, reg_offset, vf_shift; local
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/linux-master/drivers/pwm/
H A Dpwm-meson.c66 u8 reg_offset; member in struct:meson_pwm_channel_data
73 .reg_offset = REG_PWM_A,
80 .reg_offset = REG_PWM_B,
224 writel(value, meson->base + channel_data->reg_offset);
322 value = readl(meson->base + channel_data->reg_offset);
/linux-master/drivers/pci/controller/dwc/
H A Dpci-keystone.c152 u32 reg_offset; local
158 reg_offset = irq % 8;
161 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),
163 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
198 u32 reg_offset; local
206 reg_offset = irq % 8;
209 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),
222 u32 reg_offset; local
230 reg_offset = irq % 8;
233 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),
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/linux-master/drivers/clk/bcm/
H A Dclk-kona.c122 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) argument
124 return readl(ccu->base + reg_offset);
129 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) argument
131 writel(reg_val, ccu->base + reg_offset);
183 __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want) argument
192 val = __ccu_read(ccu, reg_offset);
199 ccu->name, reg_offset, bit, want ? "set" : "clear");
/linux-master/drivers/power/supply/
H A Dsbs-battery.c611 int reg_offset, enum power_supply_property psp,
617 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr);
622 if (sbs_data[reg_offset].min_value < 0)
625 if (ret >= sbs_data[reg_offset].min_value &&
626 ret <= sbs_data[reg_offset].max_value) {
797 int reg_offset, enum power_supply_property psp,
810 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr);
610 sbs_get_battery_property(struct i2c_client *client, int reg_offset, enum power_supply_property psp, union power_supply_propval *val) argument
796 sbs_get_battery_capacity(struct i2c_client *client, int reg_offset, enum power_supply_property psp, union power_supply_propval *val) argument
/linux-master/drivers/net/ethernet/cavium/thunder/
H A Dnicvf_ethtool.c368 u64 reg_offset; local
420 reg_offset = NIC_QSET_RQ_0_7_STAT_0_1 | (1 << 3);
421 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);
438 reg_offset = NIC_QSET_SQ_0_7_STAT_0_1 | (1 << 3);
439 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);
453 reg_offset = NIC_QSET_RBDR_0_1_PREFETCH_STATUS;
454 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q);
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.c402 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]);
405 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
448 cfg_reg = type->reg_offset[cfg_type];
547 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
551 writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
575 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]);
599 + type->reg_offset[PINCFG_TYPE_FUNC];
1208 const u8 *offs = bank->type->reg_offset;
1261 const u8 *offs = bank->type->reg_offset;
/linux-master/drivers/crypto/hisilicon/zip/
H A Dzip_main.c338 .reg_offset = HZIP_CORE_DFX_BASE,
341 .reg_offset = HZIP_CORE_DFX_COMP_0,
344 .reg_offset = HZIP_CORE_DFX_COMP_1,
347 .reg_offset = HZIP_CORE_DFX_DECOMP_0,
350 .reg_offset = HZIP_CORE_DFX_DECOMP_1,
353 .reg_offset = HZIP_CORE_DFX_DECOMP_2,
356 .reg_offset = HZIP_CORE_DFX_DECOMP_3,
359 .reg_offset = HZIP_CORE_DFX_DECOMP_4,
362 .reg_offset = HZIP_CORE_DFX_DECOMP_5,

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