1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
24		uint32_t sh_mem_config,
25		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
26		uint32_t sh_mem_bases, uint32_t inst);
27int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
28		unsigned int vmid, uint32_t inst);
29int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
30				uint32_t inst);
31int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
32			uint32_t queue_id, uint32_t __user *wptr,
33			uint32_t wptr_shift, uint32_t wptr_mask,
34			struct mm_struct *mm, uint32_t inst);
35int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd,
36			    uint32_t pipe_id, uint32_t queue_id,
37			    uint32_t doorbell_off, uint32_t inst);
38int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev,
39			uint32_t pipe_id, uint32_t queue_id,
40			uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
41bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
42			uint64_t queue_address, uint32_t pipe_id,
43			uint32_t queue_id, uint32_t inst);
44int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
45				enum kfd_preempt_type reset_type,
46				unsigned int utimeout, uint32_t pipe_id,
47				uint32_t queue_id, uint32_t inst);
48int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
49					uint32_t gfx_index_val,
50					uint32_t sq_cmd, uint32_t inst);
51bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
52					uint8_t vmid, uint16_t *p_pasid);
53void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,
54			uint32_t vmid, uint64_t page_table_base);
55void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
56		int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst);
57void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
58		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
59		uint32_t inst);
60void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
61				uint32_t queue_id, uint32_t inst);
62uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev,
63				uint32_t pipe_id, uint32_t queue_id);
64void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst);
65void kgd_gfx_v9_set_wave_launch_stall(struct amdgpu_device *adev,
66					uint32_t vmid,
67					bool stall);
68uint32_t kgd_gfx_v9_enable_debug_trap(struct amdgpu_device *adev,
69				      bool restore_dbg_registers,
70				      uint32_t vmid);
71uint32_t kgd_gfx_v9_disable_debug_trap(struct amdgpu_device *adev,
72					bool keep_trap_enabled,
73					uint32_t vmid);
74int kgd_gfx_v9_validate_trap_override_request(struct amdgpu_device *adev,
75					     uint32_t trap_override,
76					     uint32_t *trap_mask_supported);
77uint32_t kgd_gfx_v9_set_wave_launch_mode(struct amdgpu_device *adev,
78					uint8_t wave_launch_mode,
79					uint32_t vmid);
80uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct amdgpu_device *adev,
81					     uint32_t vmid,
82					     uint32_t trap_override,
83					     uint32_t trap_mask_bits,
84					     uint32_t trap_mask_request,
85					     uint32_t *trap_mask_prev,
86					     uint32_t kfd_dbg_trap_cntl_prev);
87uint32_t kgd_gfx_v9_set_address_watch(struct amdgpu_device *adev,
88					uint64_t watch_address,
89					uint32_t watch_address_mask,
90					uint32_t watch_id,
91					uint32_t watch_mode,
92					uint32_t debug_vmid,
93					uint32_t inst);
94uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev,
95					uint32_t watch_id);
96void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev,
97				uint32_t *wait_times,
98				uint32_t inst);
99void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev,
100					       uint32_t wait_times,
101					       uint32_t grace_period,
102					       uint32_t *reg_offset,
103					       uint32_t *reg_data);
104