1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#include "amdgpu.h" 24#include "amdgpu_atombios.h" 25#include "nbio_v6_1.h" 26 27#include "nbio/nbio_6_1_default.h" 28#include "nbio/nbio_6_1_offset.h" 29#include "nbio/nbio_6_1_sh_mask.h" 30#include "nbio/nbio_6_1_smn.h" 31#include "vega10_enum.h" 32#include <uapi/linux/kfd_ioctl.h> 33 34#define smnPCIE_LC_CNTL 0x11140280 35#define smnPCIE_LC_CNTL3 0x111402d4 36#define smnPCIE_LC_CNTL6 0x111402ec 37#define smnPCIE_LC_CNTL7 0x111402f0 38#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c 39#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L 40#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 41#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 42#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123530 43#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 44#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 45#define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 46#define smnRCC_BIF_STRAP2 0x10123488 47#define smnRCC_BIF_STRAP3 0x1012348c 48#define smnRCC_BIF_STRAP5 0x10123494 49#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 50#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 51#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 52#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 53#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 54#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 55 56static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev) 57{ 58 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 59 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 60 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 61 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 62} 63 64static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) 65{ 66 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 67 68 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 69 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 70 71 return tmp; 72} 73 74static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 75{ 76 if (enable) 77 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 78 BIF_FB_EN__FB_READ_EN_MASK | 79 BIF_FB_EN__FB_WRITE_EN_MASK); 80 else 81 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 82} 83 84static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) 85{ 86 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); 87} 88 89static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 90 bool use_doorbell, int doorbell_index, int doorbell_size) 91{ 92 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 93 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 94 95 u32 doorbell_range = RREG32(reg); 96 97 if (use_doorbell) { 98 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 99 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 100 } else 101 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 102 103 WREG32(reg, doorbell_range); 104 105} 106 107static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, 108 bool enable) 109{ 110 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 111} 112 113static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 114 bool enable) 115{ 116 u32 tmp = 0; 117 118 if (enable) { 119 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 120 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 121 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 122 123 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 124 lower_32_bits(adev->doorbell.base)); 125 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 126 upper_32_bits(adev->doorbell.base)); 127 } 128 129 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 130} 131 132 133static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, 134 bool use_doorbell, int doorbell_index) 135{ 136 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 137 138 if (use_doorbell) { 139 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 140 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 141 BIF_IH_DOORBELL_RANGE, SIZE, 6); 142 } else 143 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 144 145 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 146} 147 148static void nbio_v6_1_ih_control(struct amdgpu_device *adev) 149{ 150 u32 interrupt_cntl; 151 152 /* setup interrupt control */ 153 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 154 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 155 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 156 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 157 */ 158 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 159 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 160 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 161 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 162} 163 164static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 165 bool enable) 166{ 167 uint32_t def, data; 168 169 def = data = RREG32_PCIE(smnCPM_CONTROL); 170 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 171 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 172 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 173 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 174 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 175 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 176 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 177 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 178 } else { 179 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 180 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 181 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 182 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 183 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 184 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 185 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 186 } 187 188 if (def != data) 189 WREG32_PCIE(smnCPM_CONTROL, data); 190} 191 192static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 193 bool enable) 194{ 195 uint32_t def, data; 196 197 def = data = RREG32_PCIE(smnPCIE_CNTL2); 198 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 199 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 200 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 201 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 202 } else { 203 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 204 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 205 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 206 } 207 208 if (def != data) 209 WREG32_PCIE(smnPCIE_CNTL2, data); 210} 211 212static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, 213 u64 *flags) 214{ 215 int data; 216 217 /* AMD_CG_SUPPORT_BIF_MGCG */ 218 data = RREG32_PCIE(smnCPM_CONTROL); 219 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 220 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 221 222 /* AMD_CG_SUPPORT_BIF_LS */ 223 data = RREG32_PCIE(smnPCIE_CNTL2); 224 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 225 *flags |= AMD_CG_SUPPORT_BIF_LS; 226} 227 228static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 229{ 230 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 231} 232 233static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 234{ 235 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 236} 237 238static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) 239{ 240 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 241} 242 243static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) 244{ 245 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 246} 247 248const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { 249 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 250 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 251 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 252 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 253 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 254 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 255 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 256 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 257 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 258 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 259 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 260 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 261}; 262 263static void nbio_v6_1_init_registers(struct amdgpu_device *adev) 264{ 265 uint32_t def, data; 266 267 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 268 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 269 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 270 271 if (def != data) 272 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 273 274 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 275 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 276 277 if (def != data) 278 WREG32_PCIE(smnPCIE_CI_CNTL, data); 279 280 if (amdgpu_sriov_vf(adev)) 281 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 282 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 283} 284 285#ifdef CONFIG_PCIEASPM 286static void nbio_v6_1_program_ltr(struct amdgpu_device *adev) 287{ 288 uint32_t def, data; 289 290 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 291 292 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 293 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 294 if (def != data) 295 WREG32_PCIE(smnRCC_BIF_STRAP2, data); 296 297 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 298 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 299 if (def != data) 300 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 301 302 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 303 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 304 if (def != data) 305 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 306} 307#endif 308 309static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) 310{ 311#ifdef CONFIG_PCIEASPM 312 uint32_t def, data; 313 314 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 315 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 316 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 317 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 318 if (def != data) 319 WREG32_PCIE(smnPCIE_LC_CNTL, data); 320 321 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 322 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 323 if (def != data) 324 WREG32_PCIE(smnPCIE_LC_CNTL7, data); 325 326 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 327 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 328 if (def != data) 329 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 330 331 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 332 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 333 if (def != data) 334 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 335 336 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 337 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 338 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 339 if (def != data) 340 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 341 342 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 343 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 344 if (def != data) 345 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 346 347 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 348 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 349 if (def != data) 350 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 351 352 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 353 354 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 355 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 356 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 357 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 358 if (def != data) 359 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 360 361 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 362 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 363 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 364 if (def != data) 365 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 366 367 /* Don't bother about LTR if LTR is not enabled 368 * in the path */ 369 if (adev->pdev->ltr_path) 370 nbio_v6_1_program_ltr(adev); 371 372 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 373 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 374 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 375 if (def != data) 376 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 377 378 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 379 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 380 if (def != data) 381 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 382 383 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 384 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 385 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 386 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 387 if (def != data) 388 WREG32_PCIE(smnPCIE_LC_CNTL, data); 389 390 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 391 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 392 if (def != data) 393 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 394#endif 395} 396 397const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { 398 .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, 399 .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, 400 .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, 401 .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, 402 .get_rev_id = nbio_v6_1_get_rev_id, 403 .mc_access_enable = nbio_v6_1_mc_access_enable, 404 .get_memsize = nbio_v6_1_get_memsize, 405 .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range, 406 .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture, 407 .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture, 408 .ih_doorbell_range = nbio_v6_1_ih_doorbell_range, 409 .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating, 410 .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep, 411 .get_clockgating_state = nbio_v6_1_get_clockgating_state, 412 .ih_control = nbio_v6_1_ih_control, 413 .init_registers = nbio_v6_1_init_registers, 414 .remap_hdp_registers = nbio_v6_1_remap_hdp_registers, 415 .program_aspm = nbio_v6_1_program_aspm, 416}; 417